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zilog worldwide headquarters ? 532 race street ? san jose, ca 95126 telephone: 408.558.8500 ? fax: 408.558.8300 ? www.zilog.com preliminary ps015309-1004 ez80acclaim!? flash microcontrollers ez80f92/ez80f93 product specification
ps015309-1004 preliminary this publication is subject to replacement by a later edition. t o determine whether a later edition e xists, or to request copies of publications, contact: zilog w orldwide headquarters 532 race street san jose, ca 95126 t elephone: 408.558.8500 fax: 408.558.8300 www .zilog.com zilog is a re gistered trademark of zilog inc. in the united states and in other countries. all other products and/or service names mentioned herein may be trademarks of the companies with which the y are associated. document disclaimer ? 2004 by zilog, inc. all rights reserv ed. information in this publication concerning the de vices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does no t assume liability for or pr o vide a represent a tion of a ccura cy of the informa tion, devices, or technology described in this document . zilog also does no t assume liability for intellectu al pr oper ty infringement rela ted in any manner t o use of informa tion, devices, or technology described herein or o ther wise. except with the e xpress written appro v al zilog, use of information, de vices, or technology as critical components of life support systems is not authorized. no licenses or other rights are con v e yed, implicitly or otherwise, by this document under an y intellectual property rights.
ps015309-1004 preliminary revision history ez80f92/ez80f93 product specification iii revision history each instance in t able 1 re? ects a change to this document from its pre vious re vision. t o see more detail, click the appropriate link in the table. t able 1. revision history of this document ; date revision level section description page # october. 2 004 09 formatted to current publication standards all t imer control register clarified rst_en description s. 82 figure 57 corrected cs rise time label from t8 to t6. 229 figure 59 corrected cs rise time label from t8 to t6. 232 real-t ime clock oscillator and source selection clarified language describing rtc drive frequency. 89
ps015309-1004 preliminary table of contents ez80f92/ez80f93 product specification iv t able of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii i l ist of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ez80 ? cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 voltage brown-out reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 clock peripheral power-down registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 gpio overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 gpio operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 gpio control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 nonmaskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 chip selects and wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 memory and i/o chip selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 memory chip select operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 i/o chip select operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 wait input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ps015309-1004 preliminary table of contents ez80f92/ez80f93 product specification v chip selects during bus request/bus acknowledge cycles . . . . . . . . . . . . . . . . . . 53 bus mode controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ez80 bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 z80 bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 intel? b us mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 motorola bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 chip select registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 watch-dog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 watch-dog timer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 watch-dog timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 watch-dog timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 programmable reload timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 programmable reload timers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 programmable reload timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 programmable reload timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 real-time clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 real-time clock alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 real-time clock oscillator and source selection . . . . . . . . . . . . . . . . . . . . . . . . . . 89 real-time clock battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 real-time clock recommended operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 real-time clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 uart functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 uart functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 uart recommended usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 brg control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 uart registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 receiver frequency divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 infrared encoder/decoder signal pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 loopback testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
ps015309-1004 preliminary table of contents ez80f92/ez80f93 product specification vi serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 spi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 spi functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 spi flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 spi baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 data transfer procedure with spi configured as the master . . . . . . . . . . . . . . . . . 134 data transfer procedure with spi configured as a slave . . . . . . . . . . . . . . . . . . . 135 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 i 2 c s erial i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 i 2 c general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 transferring data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 i 2 c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 zilog debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 zdi-supported protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 zdi clock and data conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 zdi start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 zdi register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 zdi write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 zdi read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 operation of the ez80f92 device during zdi breakpoints . . . . . . . . . . . . . . . . . 167 bus requests during zdi debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 zdi write only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 zdi read only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 zdi register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 on-chip instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 introduction to on-chip instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 oci activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 oci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 oci information requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 random access memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 ram control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 flash memory arrangement in the ez80f92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 flash memory arrangement in the ez80f93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 programming flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
ps015309-1004 preliminary table of contents ez80f92/ez80f93 product specification vii erasing flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 flash control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 ez80 ? c pu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 op-code map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 on-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 20 mhz primary crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 32 khz real-time clock crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . 219 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 por and vbo electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 typical current consumption under various operating conditions . . . . . . . . . . 223 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 external memory read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 external memory write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 external i/o read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 external i/o write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 wait state timing for read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 wait state timing for write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 general purpose i/o port input sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 external bus acknowledge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 external system clock driver (phi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 zilog debug interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 part number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 precharacterization product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 document information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 document number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 change log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 customer feedback form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
ps015309-1004 preliminary list of figures ez80f92/ez80f93 product specification viii list of figures figure 1. ez80f92 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. 100-pin lqfp configuration of the ez80f92 device . . . . . . . . . . . . . . . . . . 4 figure 3. gpio port pin block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 4. example: memory chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 5. wait input sampling block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 6. example: z80 bus mode write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 7. intel ? b us mode signal and pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 8. example: intel ? bus mode read timingseparate address and d ata buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 9. example: intel ? bus mode write timingseparate address and d ata buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 10. example: intel ? bus mode read timingmultiplexed address and d ata bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 11. example: intel ? bus mode write timingmultiplexed address and d ata bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 12. motorola bus mode signal and pin mapping . . . . . . . . . . . . . . . . . . . . . . . 64 figure 13. watch-dog timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 14. prt single pass mode operation example . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 15. uart block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 16. infrared system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 17. spi master device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 18. spi slave device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 19. i 2 c clock and data relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 20. start and stop conditions in i 2 c protocol . . . . . . . . . . . . . . . . . . . . . 141 figure 21. i 2 c acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 22. clock synchronization in i 2 c protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 23. typical zdi debug setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 24. schematic for building a target board zpak ii connector . . . . . . . . . . 162 figure 25. zdi write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 26. zdi read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 27. zdi address write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 28. ez80f92 on-chip ram memory addressing example . . . . . . . . . . . . . . 189 figure 29. ez80f93 on-chip ram memory addressing example . . . . . . . . . . . . . . 190
ps015309-1004 preliminary list of figures ez80f92/ez80f93 product specification ix figure 30. recommended crystal oscillator configuration (20mhz operation) . . . . 218 figure 31. recommended crystal oscillator configuration (32khz operation) . . . . 219 figure 32. i cc v ersus wait states as a function of frequency . . . . . . . . . . . . . . . . 224 figure 33. i cc v ersus frequency as a function of wait states . . . . . . . . . . . . . . . . 225 figure 34. i cc v ersus temperature as a function of frequency . . . . . . . . . . . . . . . . 226 figure 35. i cc v ersus frequency in halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 figure 36. i cc v ersus temperature in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . 228 figure 37. external memory write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 figure 38. external i/o read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 figure 39. external i/o write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 figure 40. wait state timing for read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 figure 41. wait state timing for write operations . . . . . . . . . . . . . . . . . . . . . . . . . . 235 figure 42. port input sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
ps015309-1004 preliminary list of tables ez80f92/ez80f93 product specification x list of t ables table 2. revision history of this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii table 3. 100-pin lqfp pin identification of the ez80f92 device . . . . . . . . . . . . . . . 5 table 4. pin characteristics of the ez80f92 device . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 6. clock peripheral power-down registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 7. clock peripheral power-down register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 8. gpio mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 9. port x data register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 10. port x data direction register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 11. port x alternate registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 12. port x alternate registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 13. interrupt vector sources by priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 14. vectored interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 15. register values for memory chip select example in figure 6 . . . . . . . . . 51 table 16. z80 bus mode read states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 17. z80 bus mode write states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 18. intel ? b us mode read states (s eparate address and data buses ) . . . . . . . 57 table 19. intel ? b us mode write states (separate address and data buses) . . . . . . 58 table 20. intel ? b us mode read states (multiplexed address and data bus) . . . . . . 61 table 21. intel ? b us mode write states (multiplexed address and data bus) . . . . . 61 table 22. motorola bus mode read states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 23. motorola bus mode write states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 24. chip select x lower bound registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 25. chip select x upper bound registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 26. chip select x control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 27. chip select x bus mode control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 28. watch-dog timer approximate time-out delays . . . . . . . . . . . . . . . . . . . 74 table 29. watch-dog timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 30. watch-dog timer reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 31. prt single pass mode operation example . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 32. prt continuous mode operation example . . . . . . . . . . . . . . . . . . . . . . . . 80 table 33. prt continuous mode operation example . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 34. prt timer out operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ps015309-1004 preliminary list of tables ez80f92/ez80f93 product specification xi table 35. timer control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 36. timer data registerlow byt e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 37. t imer data registerhigh byt e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 38. timer reload registerlow byt e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 39. timer reload registerhigh byt e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 40. timer input source select registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 41. real-time clock seconds registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 42. real-time clock minutes registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 43. real-time clock hours registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 44. real-time clock day-of-the-week registe r . . . . . . . . . . . . . . . . . . . . . . . . 93 table 45. real-time clock day-of-the-month registe r . . . . . . . . . . . . . . . . . . . . . . . 94 table 46. real-time clock month registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 47. real-time clock year registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 48. real-time clock century registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 49. real-time clock alarm seconds registe r . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 50. real-time clock alarm minutes registe r . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 51. real-time clock alarm hours registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 52. real-time clock alarm day-of-the-week registe r . . . . . . . . . . . . . . . . . 101 table 53. real-time clock alarm control registe r . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 54. real-time clock control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 55. uart baud rate generator registerlow byte s . . . . . . . . . . . . . . . . . . 110 table 56. uart baud rate generator registerhigh byte s . . . . . . . . . . . . . . . . . 111 table 57. uart receive buffer register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 58. uart transmit holding register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 59. uart interrupt enable register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 60. uart interrupt identification register s . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 61. uart interrupt status codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 62. uart fifo control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 63. uart line control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 64. uart character parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 65. parity select definition for multidrop communications . . . . . . . . . . . . . . 118 table 66. uart modem control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 67. uart line status register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 68. uart modem status register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 69. uart scratch pad register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 70. irda physical layer 1.4 pulse durations specifications . . . . . . . . . . . . . . 126
ps015309-1004 preliminary list of tables ez80f92/ez80f93 product specification xii table 71. frequency divider values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 72. gpio mode selection when using the irda encoder/decoder . . . . . . . . 128 table 73. infrared encoder/decoder control register s . . . . . . . . . . . . . . . . . . . . . . . 129 table 74. spi clock phase and clock polarity operation . . . . . . . . . . . . . . . . . . . . . 132 table 75. spi baud rate generator registerlow byt e . . . . . . . . . . . . . . . . . . . . . 135 table 76. spi control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 77. spi baud rate generator registerhigh byt e (s pi_brg_h = 00b9h ) . 137 table 78. spi status registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 79. spi transmit shift registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 80. spi receive buffer registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 81. i 2 c master transmit status codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 82. i 2 c master transmit status codes for data bytes . . . . . . . . . . . . . . . . . . 147 table 83. i 2 c 10-bit master transmit status codes . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 84. i 2 c master receive status codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 85. i 2 c master receive status codes for data bytes . . . . . . . . . . . . . . . . . . . 150 table 86. i 2 c register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 87. i 2 c slave address register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 88. i 2 c data register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 89. i 2 c extended slave address register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 90. i 2 c control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 91. i 2 c status register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 92. i 2 c status codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 93. i 2 c clock control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 94. i 2 c software reset registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 95. recommended zdi clock vs. system clock frequency . . . . . . . . . . . . . . 162 table 96. zdi write only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 97. zdi read only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 98. zdi address match register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 99. zdi break control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 100. zdi master control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 101. zdi write data register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 102. zdi read/write control register function s . . . . . . . . . . . . . . . . . . . . . . . 176 table 103. zdi bus control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 104. instruction store 4:0 register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 105. zdi write memory registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 106. ez80 product id low byte registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
ps015309-1004 preliminary list of tables ez80f92/ez80f93 product specification xiii table 107. ez80 product id high byte registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 108. ez80 product id revision registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 109. zdi status registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 110. zdi read register low, high and uppe r . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 111. zdi bus control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 112. zdi read memory registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 113. oci pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 114. ram control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 115. ram address upper byte registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 116. flash key registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 117. flash address upper byte registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 118. flash data registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 119. flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 120. flash frequency divider values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 121. flash frequency divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 122. flash write/erase protection registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 123. flash interrupt control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 124. flash row select registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 125. flash page select registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 126. flash column select registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 127. flash program control registe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 128. arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 129. bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 130. block transfer and compare instructions . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 131. exchange instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 132. input/output instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 133. load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 134. logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 135. processor control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 136. program control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 137. rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 138. op code mapfirst op code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 139. op code mapsecond op code after 0cbh . . . . . . . . . . . . . . . . . . . . . . 212 table 140. op code mapsecond op code after 0ddh . . . . . . . . . . . . . . . . . . . . . 213 table 141. op code mapsecond op code after 0edh . . . . . . . . . . . . . . . . . . . . . 214 table 142. op code mapsecond op code after 0fdh . . . . . . . . . . . . . . . . . . . . . 215
ps015309-1004 preliminary list of tables ez80f92/ez80f93 product specification xiv table 143. op code mapfourth byte after 0ddh, 0cbh, and dd . . . . . . . . . . . . . 216 table 144. op code mapfourth byte after 0fdh, 0cbh, and dd . . . . . . . . . . . . . 2 17 table 145. recommended crystal oscillator specification s . . . . . . . . . . . . . . . . . . . . 219 table 146. recommended crystal oscillator specification s . . . . . . . . . . . . . . . . . . . . 220 table 147. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 148. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 149. por and vbo electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 150. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 151. external read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 table 152. external write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 table 153. external i/o read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 154. external i/o write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 table 155. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 table 156. bus acknowledge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 table 157. phi system clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 table 158. zdi timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 table 159. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 1 architectural overview the ez80f92 de vice is a high-speed single-c ycle instruction-fetch microcontroller with a maximum clock speed of 20 mhz. it is the ? rst member of zilog s ne w ez80acclaim! ? product f amily , which of fers on-chip flash program memory . the ez80f92 de vice can operate in z80-compatible addressing mode (64 kb) or full 24-bit addressing mode (16 mb). the rich peripheral set of the ez80f92 de vice mak es it suitable for a v ariety of applications including industrial control, embedded communication, and point-of-sale ter - minals. additionally , zilog of fers the ez80f93 de vice, which features scaled-do wn mem - ory options. f or purposes of clarity , this document refers to both de vices collec - ti v ely as the ez80f92 de vice, unless otherwise speci? ed. features ? single-c ycle instruction fetch, high-performance, pipelined ez80 ? cpu core 1 ? ez80f92 contains 128 kb flash memory and 8 kb sram ? ez80f93 contains 64 kb flash memory and 4 kb sram ? lo w po wer features including sleep mode, hal t mode, and selecti v e peripheral po wer -do wn control ? t w o u ar ts with independent baud rate generators ? spi with independent clock rate generator ? i 2 c with independent clock rate generator ? ird a-compliant infrared encoder/decoder ? ne w dma-lik e cpu instructions for ef ? cient block data transfer ? glueless e xternal peripheral interf ace with 4 chip selects, indi vidual w ait state gen - erators, and an e xternal w ait input pinsupports z80-, intel-, and motorola-style b uses ? fix ed-priority v ectored interrupts (both internal and e xternal) and interrupt controller ? real-t ime clock with on-chip 32 khz oscillator , selectable 50/60 hz input, and sepa - rate v dd pin for battery backup ? six 16-bit counter/t imers with clock di viders and direct input/output dri v e ? w atch-dog t imer 1. for simplicity, the term ez80 ? cpu is referred to as cpu for the bulk of this document. note:
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 2 ? 24 bits of general-purpose i/o and zdi deb ug interf aces ? 100-pin lqfp package ? 3.0C3.6 v supply v oltage with 5 v tolerant inputs ? operating t emperature range: C standard: 0oc to +70oc C extended: C40oc to +105oc all signals with an o v erline are acti v e lo w . f or e xample, b/ w , for which w ord is acti v e lo w , and b /w , for which byte is acti v e lo w . po wer connections follo w these con v entional descriptions: block diagram figure 1 illustrates a block diagram of the ez80f92 processor . connection circuit device power v cc v dd ground gnd v ss note:
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 3 figure 1. ez80f92 block diagram ez8 0 ? jtag/zdi debug interface jtag / zdi signals (5) i 2 c serial interface scl sda spi serial parallel interface sck ss miso mosi uart universal asynchronous cts0/1 dcd0/1 dsr0/1 dtr0/1 ri0/1 rts0/1 rxd0/1 txd0/1 receiver/ transmitter (2) crystal x in x out phi oscillator and system clock generator gpio 8-bit general purpose i/o port (3) pb[7:0] pc[7:0] pd[7:0] real-time clock and programmable reload timer/counter (6) wdt watchdog timer chip select & wait state generator cs0 cs1 cs2 cs3 cpu controller data[7:0] addr[23:0] data[7:0] addr[23:0] busack busreq wait instrd iorq nmi mreq rd reset wr interrupt controller interrupt vector [7:0] bus t0_in t4_out t5_out rtc_xin rtc_xout 32 khz oscillator rtc_vdd halt_slp irda encoder/ decoder ir_txd ir_rxd t1_in t2_in t3_in 128 kb/64 kb flash memory 8kb/4kb sram
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 4 pin description figure 2 illustrates the pin layout of the ez80f92 de vice in the 100-pin lqfp package. t able 2 describes the pins and their functions. figure 2. 100-pin lqfp configuration of the ez80f92 device pd7/ ri0 pd6/ dcd0 pd5/ dsr0 pd4/ dtr0 pd3/ cts0 pd2/ r ts0 pd1/rxd0/ ir_rxd pd0/txd0/ ir_txd v dd tdi trigout tck tms v ss r tc_v dd r tc_xout r tc_xin v ss v dd busack busreq nmi reset phi scl sda v ss pb7/mosi pb6/miso pb5/t5_out pb4/t4_out pb3/sck pb2/ ss pb1/t1_in pb0/t0_in v dd x out x in v ss pc7/ ri1 pc6/ dcd1 pc5/ dsr1 pc4/ dtr1 pc3/ cts1 pc2// rts1 pc1/rxd1 pc0/txd1 addr0 addr1 addr2 addr3 addr4 addr5 v dd v ss addr6 addr7 addr8 addr9 addr10 addr1 1 addr12 addr13 addr14 v dd v ss addr15 addr16 addr17 addr18 addr19 addr20 addr21 addr22 addr23 cs0 cs1 cs2 cs3 v dd v ss da t a0 da t a1 da t a2 da t a3 da t a4 da t a5 da t a6 da t a7 v dd v ss iorq mreq rd wr instrd wait 100-pin lqfp 1 10 80 90 100 tdo v dd halt_slp 91 92 93 94 95 96 97 98 99 81 82 83 84 85 86 87 88 89 76 77 78 79 9 8 7 6 5 4 3 2 1 1 20 19 18 17 16 15 14 13 12 21 25 24 23 22 30 40 50 41 42 43 44 45 46 47 48 49 31 32 33 34 35 36 37 38 39 26 27 28 29 51 60 59 58 57 56 55 54 53 52 61 70 69 68 67 66 65 64 63 62 71 75 74 73 72
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 5 t able 2. 100-pin lqfp pin identification of the ez80f92 device pin # symbol function signal direction description 1 addr0 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 2 addr1 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 3 addr2 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 4 addr3 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 5 addr4 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 6 addr5 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects.
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 6 7 v dd power supply power supply. 8 v ss ground ground. 9 addr6 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 10 addr7 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 11 addr8 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 12 addr9 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 13 addr10 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 7 14 addr11 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 15 addr12 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 16 addr13 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 17 addr14 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 18 v dd power supply power supply. 19 v ss ground ground. 20 addr15 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 8 21 addr16 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 22 addr17 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 23 addr18 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 24 addr19 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 25 addr20 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 26 addr21 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 9 27 addr22 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 28 addr23 address bus bidirectional configured as an output in normal operation. the address bus selects a location in memory or i/o space to be read or written. configured as an input during bus acknowledge cycles. drives the chip select/wait state generator block to generate chip selects. 29 cs0 chip select 0 output, active low cs0 low indicates that an access is occurring in the defined cs0 memory or i/ o address space. 30 cs1 chip select 1 output, active low cs1 low indicates that an access is occurring in the defined cs1 memory or i/ o address space. 31 cs2 chip select 2 output, active low cs2 low indicates that an access is occurring in the defined cs2 memory or i/ o address space. 32 cs3 chip select 3 output, active low cs3 low indicates that an access is occurring in the defined cs3 memory or i/ o address space. 33 v dd power supply power supply. 34 v ss ground ground. 35 data0 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the ez80acclaim! ? drives these lines only during write cycles when the cpu is the bus master. 36 data1 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the cpu drives these lines only during write cycles when the cpu is the bus master. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 10 37 data2 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the cpu drives these lines only during write cycles when the cpu is the bus master. 38 data3 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the cpu drives these lines only during write cycles when the cpu is the bus master. 39 data4 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the cpu drives these lines only during write cycles when the cpu is the bus master. 40 data5 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the cpu drives these lines only during write cycles when the cpu is the bus master. 41 data6 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the cpu drives these lines only during write cycles when the cpu is the bus master. 42 data7 data bus bidirectional the data bus transfers data to and from i/o and memory devices. the cpu drives these lines only during write cycles when the cpu is the bus master. 43 v dd power supply power supply. 44 v ss ground ground. 45 iorq input/output request bidirectional, active low iorq indicates that the cpu is accessing a location in i/o space. rd and wr indicate the type of access. i t is an input in bus acknowledge cycles. 46 mreq memory request bidirectional, active low mreq low indicates that the cpu is accessing a location in memory. the rd , wr , and instrd signals indicate the type of access. i t is an input in bus acknowledge cycles. 47 rd read output, active low rd low indicates that the cpu is reading from the current address location. this pin is tristated during bus acknowledge cycles. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 11 48 wr write output, active low wr indicates that the cpu is writing to the current address location. this pin is tristated during bus acknowledge cycles. 49 instrd instruction read indicator output, active low instrd (with mreq and rd ) indicates the cpu is fetching an instruction from memory. this pin is tristated during bus acknowledge cycles. 50 w ait wait request input, active low driving the wait pin low forces the cpu to wait additional clock cycles for an external peripheral or external memory to complete its read or write operation. 51 reset system reset schmitt trigger input, active low this signal is used to initialize the cpu. this input must be low for a minimum of 3 system clock cycles, and must be held low until the clock is stable. this input includes a schmitt trigger to allow rc rise times. 52 nmi nonmaskable interrupt schmitt trigger input, active low the nmi input is a higher priority input than the maskable interrupts. it is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. this input includes a schmitt trigger to allow rc rise times. 53 busreq bus request input, active low external devices can request the cpu to release the memory interface bus for their use, by driving this pin low. 54 busack bus acknowledge output, active low the cpu responds to a low on busreq , by tristating the address, data, and control signals, and by driving the busack line low. during bus acknowledge cycles addr[23:0], iorq , and mreq are inputs. 55 hal t_slp halt and sleep indicator output, active low a low on this pin indicates that the cpu has entered either halt or sleep mode because of execution of either a halt or slp instruction. 56 v dd power supply power supply. 57 v ss ground ground. 58 rtc_x in real-time clock crystal input input this pin is the input to the low-power 32 khz crystal oscillator for the real-time clock. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 12 59 rtc_x out real-time clock crystal output bidirectional this pin is the output from the low-power 32 khz crystal oscillator for the real-time clock. this pin is an input when the rtc is configured to operate from 50/60 hz input clock signals and the 32 khz crystal oscillator is disabled. 60 rtc_ v dd real-time clock power supply power supply for the real-time clock and associated 32 khz oscillator. isolated from the power supply to the remainder of the chip. a battery can be connected to this pin to supply constant power to the real-time clock and 32 khz oscillator. 61 v ss ground ground. 62 tms jtag test mode select input jtag mode select input. 63 tck jtag test clock input jtag and zdi clock input. 64 trigout jtag test trigger output output active high trigger event indicator. 65 tdi jtag test data in bidirectional jtag data input pin. functions as zdi data i/o pin when jtag is disabled. 66 tdo jtag test data out output jtag data output pin. 67 v dd power supply power supply. 68 pd0 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. txd0 uart transmit data output this pin is used by the uart to transmit asynchronous serial data. this signal is multiplexed with pd0. ir_txd irda transmit data output this pin is used by the irda encoder/ decoder to transmit serial data. this signal is multiplexed with pd0. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 13 69 pd1 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. rxd0 receive data input this pin is used by the uart to receive asynchronous serial data. this signal is multiplexed with pd1. ir_rxd irda receive data input this pin is used by the irda encoder/ decoder to receive serial data. this signal is multiplexed with pd1. 70 pd2 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. r ts0 request to send output, active low modem control signal from uart. this signal is multiplexed with pd2. 71 pd3 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. cts0 clear to send input, active low modem status signal to the uart. this signal is multiplexed with pd3. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 14 72 pd4 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. dtr0 data terminal ready output, active low modem control signal to the uart. this signal is multiplexed with pd4. 73 pd5 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. dsr0 data set ready input, active low modem status signal to the uart. this signal is multiplexed with pd5. 74 pd6 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. dcd0 data carrier detect input, active low modem status signal to the uart. this signal is multiplexed with pd6. 75 pd7 gpio port d bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port d pin, when programmed as output, can be selected to be an open-drain or open- source output. port d is multiplexed with one uart. ri0 ring indicator input, active low modem status signal to the uart. this signal is multiplexed with pd7. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 15 76 pc0 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. txd1 transmit data output this pin is used by the uart to transmit asynchronous serial data. this signal is multiplexed with pc0. 77 pc1 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. rxd1 receive data input this pin is used by the uart to receive asynchronous serial data. this signal is multiplexed with pc1. 78 pc2 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. r ts1 request to send output, active low modem control signal from uart. this signal is multiplexed with pc2. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 16 79 pc3 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. cts1 clear to send input, active low modem status signal to the uart. this signal is multiplexed with pc3. 80 pc4 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. dtr1 data terminal ready output, active low modem control signal to the uart. this signal is multiplexed with pc4. 81 pc5 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. dsr1 data set ready input, active low modem status signal to the uart. this signal is multiplexed with pc5. 82 pc6 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. dcd1 data carrier detect input, active low modem status signal to the uart. this signal is multiplexed with pc6. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 17 83 pc7 gpio port c bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port c pin, when programmed as output, can be selected to be an open-drain or open- source output. port c is multiplexed with one uart. ri1 ring indicator input, active low modem status signal to the uart. this signal is multiplexed with pc7. 84 v ss ground ground. 85 x in system clock oscillator input input this pin is the input to the onboard crystal oscillator for the primary system clock. if an external oscillator is used, its clock output should be connected to this pin. when a crystal is used, it should be connected between x in and x out . 86 x out system clock oscillator output output this pin is the output of the onboard crystal oscillator. when used, a crystal should be connected between x in and x out . 87 v dd power supply power supply. 88 pb0 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. t0_in timer 0 in input alternate clock source for programmable reload timers 0 and 2. this signal is multiplexed with pb0. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 18 89 pb1 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. t1_in timer 1 in input alternate clock source for programmable reload timers 1 and 3. this signal is multiplexed with pb1. 90 pb2 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. ss slave select input, active low the slave select input line is used to select a slave device in spi mode. this signal is multiplexed with pb2. 91 pb3 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. sck spi serial clock bidirectional spi serial clock. this signal is multiplexed with pb3. 92 pb4 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. t4_out timer 4 out output programmable reload timer 4 timer-out signal. this signal is multiplexed with pb4. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 19 93 pb5 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. t5_out timer 5 out output programmable reload timer 5 timer-out signal. this signal is multiplexed with pb5. 94 pb6 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. miso master in, slave out bidirectional the miso line is configured as an input when the cpu is an spi master device and as an output when cpu is an spi slave device. this signal is multiplexed with pb6. 95 pb7 gpio port b bidirectional this pin can be used for general-purpose i/ o. it can be individually programmed as input or output and can also be used individually as an interrupt input. each port b pin, when programmed as output, can be selected to be an open-drain or open- source output. mosi master out, slave in bidirectional the mosi line is configured as an output when the cpu is an spi master device and as an input when the cpu is an spi slave device. this signal is multiplexed with pb7. 96 v dd power supply power supply. 97 v ss ground ground. 98 sda i 2 c serial data bidirectional this pin carries the i 2 c data signal. 99 scl i 2 c serial clock bidirectional this pin is used to receive and transmit the i 2 c clock. 100 phi system clock output this pin is an output driven by the internal system clock. t able 2. 100-pin lqfp pin identification of the ez80f92 device (continued) pin # symbol function signal direction description
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 20 pin characteristics t able 3 describes the characteristics of each pin in the ez80f92 de vice s 100-pin lqfp package. t able 3. pin characteristics of the ez80f92 device pin # symbol direction reset direction active low/high t ristate output pull up/down schmitt t rigger input open drain/ source 1 addr0 i/o o n/a y es no no no 2 addr1 i/o o n/a y es no no no 3 addr2 i/o o n/a y es no no no 4 addr3 i/o o n/a y es no no no 5 addr4 i/o o n/a y es no no no 6 addr5 i/o o n/a y es no no no 7 v dd 8 v ss 9 addr6 i/o o n/a y es no no no 10 addr7 i/o o n/a y es no no no 11 addr8 i/o o n/a y es no no no 12 addr9 i/o o n/a y es no no no 13 addr10 i/o o n/a y es no no no 14 addr11 i/o o n/a y es no no no 15 addr12 i/o o n/a y es no no no 16 addr13 i/o o n/a y es no no no 17 addr14 i/o o n/a y es no no no 18 v dd 19 v ss 20 addr15 i/o o n/a y es no no no 21 addr16 i/o o n/a y es no no no 22 addr17 i/o o n/a y es no no no 23 addr18 i/o o n/a y es no no no 24 addr19 i/o o n/a y es no no no note: i = input, o = output, i/o = input and output, u = undefined.
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 21 25 addr20 i/o o n/a y es no no no 26 addr21 i/o o n/a y es no no no 27 addr22 i/o o n/a y es no no no 28 addr23 i/o o n/a y es no no no 29 cs0 o o low no no no no 30 cs1 o o low no no no no 31 cs2 o o low no no no no 32 cs3 o o low no no no no 33 v dd 34 v ss 35 data0 i/o i n/a y es no no no 36 data1 i/o i n/a y es no no no 37 data2 i/o i n/a y es no no no 38 data3 i/o i n/a y es no no no 39 data4 i/o i n/a y es no no no 40 data5 i/o i n/a y es no no no 41 data6 i/o i n/a y es no no no 42 data7 i/o i n/a y es no no no 43 v dd 44 v ss 45 iorq i/o o low y es no no no 46 mreq i/o o low y es no no no 47 rd o o low y es no no no 48 wr o o low y es no no no 49 instrd o o low no no no no 50 w ait i i low n/a no no n/a 51 reset i i low n/a no y es n/a t able 3. pin characteristics of the ez80f92 device (continued) pin # symbol direction reset direction active low/high t ristate output pull up/down schmitt t rigger input open drain/ source note: i = input, o = output, i/o = input and output, u = undefined.
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 22 52 nmi i i low n/a no y es n/a 53 busreq i i low n/a no no n/a 54 busack o o low no no no no 55 hal t_slp o o low no no no no 56 v dd 57 v ss 58 rtc_x in i i n/a n/a no no n/a 59 rtc_x out i/o u n/a n/a no no no 60 rtc_ v dd 61 v ss 62 tms i i n/a n/a up no n/a 63 tck i i rising (in) falling (out) n/a up no n/a 64 trigout o o high no no no no 65 tdi i/o i n/a y es no no no 66 tdo o u n/a y es no no no 67 v dd 68 pd0 i/o i n/a y es no no od & os 69 pd1 i/o i n/a y es no no od & os 70 pd2 i/o i n/a y es no no od & os 71 pd3 i/o i n/a y es no no od & os 72 pd4 i/o i n/a y es no no od & os 73 pd5 i/o i n/a y es no no od & os 74 pd6 i/o i n/a y es no no od & os 75 pd7 i/o i n/a y es no no od & os 76 pc0 i/o i n/a y es no no od & os 77 pc1 i/o i n/a y es no no od & os t able 3. pin characteristics of the ez80f92 device (continued) pin # symbol direction reset direction active low/high t ristate output pull up/down schmitt t rigger input open drain/ source note: i = input, o = output, i/o = input and output, u = undefined.
ps015309-1004 preliminary architectural overview ez80f92/ez80f93 product specification 23 78 pc2 i/o i n/a y es no no od & os 79 pc3 i/o i n/a y es no no od & os 80 pc4 i/o i n/a y es no no od & os 81 pc5 i/o i n/a y es no no od & os 82 pc6 i/o i n/a y es no no od & os 83 pc7 i/o i n/a y es no no od & os 84 v ss 85 x in i i n/a n/a no no n/a 86 x out o o n/a no no no no 87 v dd 88 pb0 i/o i n/a y es no no od & os 89 pb1 i/o i n/a y es no no od & os 90 pb2 i/o i n/a y es no no od & os 91 pb3 i/o i n/a y es no no od & os 92 pb4 i/o i n/a y es no no od & os 93 pb5 i/o i n/a y es no no od & os 94 pb6 i/o i n/a y es no no od & os 95 pb7 i/o i n/a y es no no od & os 96 v dd 97 v ss 98 sda i/o i n/a y es up no od 99 scl i/o i n/a y es up no od 100 phi o o n/a y es no no no t able 3. pin characteristics of the ez80f92 device (continued) pin # symbol direction reset direction active low/high t ristate output pull up/down schmitt t rigger input open drain/ source note: i = input, o = output, i/o = input and output, u = undefined.
ps015309-1004 preliminary register map ez80f92/ez80f93 product specification 24 register map all on-chip peripheral re gisters are accessed in the i/o address space. all i/o operations emplo y 16-bit addresses. the upper byte of the 24-bit address b us is unde? ned during all i/o operations (addr[23:16] = uu ). all i/o operations using 16-bit addresses within the range 0080h?0ffh are routed to the on-chip peripherals. external i/o chip selects are not generated if the address space programmed for the i/o chip selects o v erlaps the 0080h?0ffh address range. re gisters at unused addresses within the 0080h?0ffh range assigned to on-chip periph - erals are not implemented. read access to such addresses returns unpredictable v alues and write access produces no ef fect. t able 4 diagrams the re gister map for the ez80f92 de vice. t able 4. register map address (hex) mnemonic name reset (hex) cpu access page # programmable reload counter/t imers 0080 tmr0_ctl timer 0 control register 00 r/w 83 0081 tmr0_dr_l timer 0 data registerlow byte 00 r 84 tmr0_rr_l timer 0 reload registerlow byte 00 w 85 0082 tmr0_dr_h timer 0 data registerhigh byte 00 r 85 tmr0_rr_h timer 0 reload registerhigh byte 00 w 86 0083 tmr1_ctl timer 1 control register 00 r/w 83 0084 tmr1_dr_l timer 1 data registerlow byte 00 r 84 tmr1_rr_l timer 1 reload registerlow byte 00 w 85 0085 tmr1_dr_h timer 1 data registerhigh byte 00 r 85 tmr1_rr_h timer 1 reload registerhigh byte 00 w 86 0086 tmr2_ctl timer 2 control register 00 r/w 83 notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read only if r tc registers are locked; read/w rite if r tc registers are unlocked. 4. after an external pin reset or a w atch-dog t imer reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b. 5. read only if flash memory is locked. read/w rite if flash memory is unlocked.
ps015309-1004 preliminary register map ez80f92/ez80f93 product specification 25 programmable reload counter/t imers (continued) 0087 tmr2_dr_l timer 2 data registerlow byte 00 r 84 tmr2_rr_l timer 2 reload registerlow byte 00 w 85 0088 tmr2_dr_h timer 2 data registerhigh byte 00 r 85 tmr2_rr_h timer 2 reload registerhigh byte 00 w 86 0089 tmr3_ctl timer 3 control register 00 r/w 83 008a tmr3_dr_l timer 3 data registerlow byte 00 r 84 tmr3_rr_l timer 3 reload registerlow byte 00 w 85 008b tmr3_dr_h timer 3 data registerhigh byte 00 r 85 tmr3_rr_h timer 3 reload registerhigh byte 00 w 86 008c tmr4_ctl timer 4 control register 00 r/w 83 008d tmr4_dr_l timer 4 data registerlow byte 00 r 84 tmr4_rr_l timer 4 reload registerlow byte 00 w 85 008e tmr4_dr_h timer 4 data registerhigh byte 00 r 85 tmr4_rr_h timer 4 reload registerhigh byte 00 w 86 008f tmr5_ctl timer 5 control register 00 r/w 83 0090 tmr5_dr_l timer 5 data registerlow byte 00 r 84 tmr5_rr_l timer 5 reload registerlow byte 00 w 85 0091 tmr5_dr_h timer 5 data registerhigh byte 00 r 85 tmr5_rr_h timer 5 reload registerhigh byte 00 w 86 0092 tmr_iss timer input source select register 00 r/w 87 t able 4. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read only if r tc registers are locked; read/w rite if r tc registers are unlocked. 4. after an external pin reset or a w atch-dog t imer reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b. 5. read only if flash memory is locked. read/w rite if flash memory is unlocked.
ps015309-1004 preliminary register map ez80f92/ez80f93 product specification 26 w atch-dog t imer 0093 wdt_ctl watch-dog timer control register 1 00/20 r/w 75 0094 wdt_rr watch-dog timer reset register xx w 76 general-purpose input/output ports 009a pb_dr port b data register 2 xx r/w 44 009b pb_ddr port b data direction register ff r/w 45 009c pb_alt1 port b alternate register 1 00 r/w 45 009d pb_alt2 port b alternate register 2 00 r/w 45 009e pc_dr port c data register 2 xx r/w 44 009f pc_ddr port c data direction register ff r/w 45 00a0 pc_alt1 port c alternate register 1 00 r/w 45 00a1 pc_alt2 port c alternate register 2 00 r/w 45 00a2 pd_dr port d data register 2 xx r/w 44 00a3 pd_ddr port d data direction register ff r/w 45 00a4 pd_alt1 port d alternate register 1 00 r/w 45 00a5 pd_alt2 port d alternate register 2 00 r/w 45 chip select/w ait state generator 00a8 cs0_lbr chip select 0 lower bound register 00 r/w 68 00a9 cs0_ubr chip select 0 upper bound register ff r/w 69 00aa cs0_ctl chip select 0 control register e8 r/w 70 00ab cs1_lbr chip select 1 lower bound register 00 r/w 68 00ac cs1_ubr chip select 1 upper bound register 00 r/w 69 00ad cs1_ctl chip select 1 control register 00 r/w 70 t able 4. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read only if r tc registers are locked; read/w rite if r tc registers are unlocked. 4. after an external pin reset or a w atch-dog t imer reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b. 5. read only if flash memory is locked. read/w rite if flash memory is unlocked.
ps015309-1004 preliminary register map ez80f92/ez80f93 product specification 27 chip select/w ait state generator (continued) 00ae cs2_lbr chip select 2 lower bound register 00 r/w 68 00af cs2_ubr chip select 2 upper bound register 00 r/w 69 00b0 cs2_ctl chip select 2 control register 00 r/w 70 00b1 cs3_lbr chip select 3 lower bound register 00 r/w 68 00b2 cs3_ubr chip select 3 upper bound register 00 r/w 69 00b3 cs3_ctl chip select 3 control register 00 r/w 70 on-chip ram control 00b4 ram_ctl ram control register 80 r/w 191 00b5 ram_addr_u ram address upper byte register ff r/w 191 serial peripheral interface ( spi) block 00b8 spi_brg_l spi baud rate generator registerlow byte 02 r/w 135 00b9 spi_brg_h spi baud rate generator registerhigh byte 00 r/w 137 00ba spi_ctl spi control register 04 r/w 137 00bb spi_sr spi status register 00 r 138 00bc spi_tsr spi transmit shift register xx w 139 spi_rbr spi receive buffer register xx r 139 infrared encoder/decoder block 00bf ir_ctl infrared encoder/decoder control 00 r/w 129 t able 4. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read only if r tc registers are locked; read/w rite if r tc registers are unlocked. 4. after an external pin reset or a w atch-dog t imer reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b. 5. read only if flash memory is locked. read/w rite if flash memory is unlocked.
ps015309-1004 preliminary register map ez80f92/ez80f93 product specification 28 universal asynchronous receiver/t ransmitter 0 (uart0) block 00c0 uart0_rbr uart 0 receive buffer register xx r 1 12 uart0_thr uart 0 transmit holding register xx w 1 12 uart0_brg_l uart 0 baud rate generator register low byte 02 r/w 1 10 00c1 uart0_ier uart 0 interrupt enable register 00 r/w 1 13 uart0_brg_h uart 0 baud rate generator register high byte 00 r/w 1 1 1 00c2 uart0_iir uart 0 interrupt identification register 01 r 1 14 uart0_fctl uart 0 fifo control register 00 w 1 15 00c3 uart0_lctl uart 0 line control register 00 r/w 1 16 00c4 uart0_mctl uart 0 modem control register 00 r/w 1 19 00c5 uart0_lsr uart 0 line status register 60 r 120 00c6 uart0_msr uart 0 modem status register xx r 122 00c7 uart0_spr uart 0 scratch pad register 00 r/w 123 i 2 c block 00c8 i2c_sar i 2 c slave address register 00 r/w 153 00c9 i2c_xsar i 2 c extended slave address register 00 r/w 154 00ca i2c_dr i 2 c data register 00 r/w 154 00cb i2c_ctl i 2 c control register 00 r/w 156 00cc i2c_sr i 2 c status register f8 r 157 i2c_ccr i 2 c clock control register 00 w 159 00cd i2c_srr i 2 c software reset register xx w 160 t able 4. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read only if r tc registers are locked; read/w rite if r tc registers are unlocked. 4. after an external pin reset or a w atch-dog t imer reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b. 5. read only if flash memory is locked. read/w rite if flash memory is unlocked.
ps015309-1004 preliminary register map ez80f92/ez80f93 product specification 29 universal asynchronous receiver/t ransmitter 1 (uart1) block 00d0 uart1_rbr uart 1 receive buffer register xx r 1 12 uart1_thr uart 1 transmit holding register xx w 1 12 uart1_brg_l uart 1 baud rate generator register low byte 02 r/w 1 10 00d1 uart1_ier uart 1 interrupt enable register 00 r/w 1 13 uart1_brg_h uart 1 baud rate generator register high byte 00 r/w 1 1 1 00d2 uart1_iir uart 1 interrupt identification register 01 r 1 14 uart1_fctl uart 1 fifo control register 00 w 1 15 00d3 uart1_lctl uart 1 line control register 00 r/w 1 16 00d4 uart1_mctl uart 1 modem control register 00 r/w 1 19 00d5 uart1_lsr uart 1 line status register 60 r/w 120 00d6 uart1_msr uart 1 modem status register xx r/w 122 00d7 uart1_spr uart 1 scratch pad register 00 r/w 123 low-power control 00db clk_ppd1 clock peripheral power-down register 1 00 r/w 38 00dc clk_ppd2 clock peripheral power-down register 2 00 r/w 39 real-t ime clock 00e0 rtc_sec rtc seconds register 3 xx r/w 90 00e1 rtc_min rtc minutes register 3 xx r/w 91 00e2 rtc_hrs rtc hours register 3 xx r/w 92 00e3 rtc_dow rtc day-of-the-week register 3 0x r/w 93 t able 4. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read only if r tc registers are locked; read/w rite if r tc registers are unlocked. 4. after an external pin reset or a w atch-dog t imer reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b. 5. read only if flash memory is locked. read/w rite if flash memory is unlocked.
ps015309-1004 preliminary register map ez80f92/ez80f93 product specification 30 real-t ime clock (continued) 00e4 rtc_dom rtc day-of-the-month register 3 xx r/w 94 00e5 rtc_mon rtc month register 3 xx r/w 95 00e6 rtc_yr rtc year register 3 xx r/w 96 00e7 rtc_cen rtc century register 3 xx r/w 97 00e8 rtc_asec rtc alarm seconds register xx r/w 98 00e9 rtc_amin rtc alarm minutes register xx r/w 99 00ea rtc_ahrs rtc alarm hours register xx r/w 100 00eb rtc_adow rtc alarm day-of-the-week register 0x r/w 101 00ec rtc_actrl rtc alarm control register 00 r/w 102 00ed rtc_ctrl rtc control register 4 x0xxx000b/ x0xxxx10b r/w 103 chip select bus mode control 00f0 cs0_bmc chip select 0 bus mode control register 02 r/w 71 00f1 cs1_bmc chip select 1 bus mode control register 02 r/w 71 00f2 cs2_bmc chip select 2 bus mode control register 02 r/w 71 00f3 cs3_bmc chip select 3 bus mode control register 02 r/w 71 flash memory control registers 00f5 flash_key flash key register 00 w 197 00f6 flash_data flash data register xx r/w 198 00f7 flash_addr_u flash address upper byte register 0 r/w 198 00f8 flash_ctrl flash control register 88 r/w 199 00f9 flash_fdiv flash frequency divider register 5 01 r/w 200 00fa flash_prot flash write/erase protection register 5 ff r/w 201 t able 4. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read only if r tc registers are locked; read/w rite if r tc registers are unlocked. 4. after an external pin reset or a w atch-dog t imer reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b. 5. read only if flash memory is locked. read/w rite if flash memory is unlocked.
ps015309-1004 preliminary register map ez80f92/ez80f93 product specification 31 flash memory control registers (continued) 00fb flash_irq flash interrupt control register 00 r/w 203 00fc flash_page flash page select register 00 r/w 204 00fd flash_row flash row select register 00 r/w 204 00fe flash_col flash column select register 00 r/w 205 00ff flash_pgctl flash program control register 00 r/w 206 t able 4. register map (continued) address (hex) mnemonic name reset (hex) cpu access page # notes: 1. after an external pin reset, the w atch-dog t imer control register is reset to 00h. after a w atch-dog t imer time- out reset, the w atch-dog t imer control register is reset to 20h. 2. when the cpu reads this register , the current sampled value of the port is read. 3. read only if r tc registers are locked; read/w rite if r tc registers are unlocked. 4. after an external pin reset or a w atch-dog t imer reset, the r tc control register is reset to x0xxxx00b. after an r tc alarm sleep-mode recovery reset, the r tc control register is reset to x0xxxx10b. 5. read only if flash memory is locked. read/w rite if flash memory is unlocked.
ps015309-1004 preliminary ez80 ? cpu core ez80f92/ez80f93 product specification 32 ez80 ? cpu core the ez80 ? is the ? rst 8-bit cpu to support 16 mb linear addressing. each softw are mod - ule or task under a real-time e x ecuti v e or operating system can operate in z80-compatible (64 kb) mode or full 24-bit (16 mb) address mode. the cpu instruction set is a superset of the instruction sets for the z80 and z180 cpus. z80 and z180 programs can be e x ecuted on an ez80 ? cpu with little or no modi? cation. features ? code-compatible with z80 and z180 products ? 24-bit linear address space ? single-c ycle instruction fetch ? pipelined fetch, decode, and e x ecute ? dual stack pointers for adl (24-bit) and z80 (16-bit) memory modes ? 24-bit cpu re gisters and alu (arithmetic logic unit) ? deb ug support ? nonmaskable interrupt ( nmi), plus support for 128 maskable v ectored interrupts f or more information about the ez80 ? cpu and its instruction set, please refer to the ez80 cpu user manual (um0077).
ps015309-1004 preliminary reset ez80f92/ez80f93 product specification 33 reset reset operation the reset controller within the ez80f92 de vice pro vides a consistent reset function for all types of resets that can af fect the system. a system reset, referred to in this document as reset , returns the ez80f92 de vice to a de? ned state. all internal re gisters af fected by reset return to their def ault conditions. reset con? gures the gpio port pins as inputs and clears the cpu s program counter to 000000h . program code e x ecution ceases dur - ing reset . the e v ents that can cause a reset are: ? po wer -on reset ( por) ? lo w- v oltage bro wn-out ( vbo) ? external reset pin assertion ? w atch-dog t imer ( wdt) time-out when con? gured to generate a reset ? real-t ime clock alarm with the cpu in lo w-po wer sleep mode ? ex ecution of a deb ug reset command during a reset , an internal reset mode timer holds the system in reset mode for 257 system clock ( sclk) c ycles. the reset mode timer be gins incrementing on the ne xt rising edge of sclk follo wing deacti v ation of all reset e v ents. the user must determine if 257 sclk c ycles pro vides suf ? cient time for the pri - mary crystal oscillator to stabilize. power-on reset a po wer -on reset (por) occurs each time the supply v oltage to the part rises from belo w the v oltage bro wn-out threshold to abo v e the por v oltage threshold (v por ). the internal bandg ap-referenced v oltage detector sends a continuous reset signal to the reset con - troller until the supply v oltage ( v cc ) e xceeds the por v oltage threshold. after v cc rises abo v e v por , an on-chip analog delay element brie? y maintains the reset signal to the reset controller (t an a ). after this analog delay , the ez80f92 de vice is in reset mode until the reset mode timer e xpires. por operation is illustrated in figure 3 . the signals in this ? gure are not dra wn to scale and are for illustration purposes only . note:
ps015309-1004 preliminary reset ez80f92/ez80f93 product specification 34 voltage brown-out reset if, after program e x ecution be gins, the supply v oltage ( v cc ) drops belo w the v oltage bro wn-out threshold ( v vbo ), the ez80f92 de vice resets. the vbo protection circuitry detects the lo w supply v oltage and initiates the reset via the reset controller . the ez80f92 de vice remains in reset mode until the supply v oltage ag ain returns abo v e the por v oltage threshold (v por ) and the reset controller releases the internal reset sig - nal. the vbo circuitry rejects v ery short ne g ati v e bro wn-out pulses to pre v ent spurious reset e v ents. vbo operation is illustrated in figure 4 . the signals in this ? gure are not dra wn to scale and are for illustration purposes only . figure 3. power-on reset operation v por t ana v vbo v = 0.0v cc v = 3.3v cc system clock internal reset signal oscillator startup program execution reset mode timer delay
ps015309-1004 preliminary reset ez80f92/ez80f93 product specification 35 figure 4. v oltage brown-out reset operation v por t ana v vbo v = 3.3v v = 3.3v cc cc system clock internal reset signal v oltage brown-out program execution program execution reset mode timer delay
ps015309-1004 preliminary low-power modes ez80f92/ez80f93 product specification 36 low-power modes overview the ez80f92 de vice pro vides a range of po wer -sa ving features. the highest le v el of po wer reduction is pro vided by sleep mode. the ne xt le v el of po wer reduction is pro - vided by the hal t instruction. the lo west le v el of po wer reduction is pro vided by the clock peripheral po wer -do wn re gisters. sleep mode ex ecution of the cpu s sleep instruction (slp) places the ez80f92 de vice into sleep mode. in sleep mode, the operating characteristics are: ? the primary crystal oscillator is disabled ? the system clock is disabled ? the cpu is idle ? the program counter (pc) stops incrementing ? the 32 khz crystal oscillator continues to operate and dri v e the real-t ime clock and the w atch-dog t imer (if wdt is con? gured to operate from the 32 khz oscillator) the cpu can be brought out of sleep mode by an y of the follo wing operations: ? a reset via the e xternal reset pin dri v en lo w ? a reset via a real-t ime clock alarm ? a reset via e x ecution of a deb ug reset command after e xiting sleep mode, the standard reset delay occurs to allo w the primary crystal oscillator to stabilize. refer to the reset section on page 33 for more information. during sleep mode, the cpu freezes the last address a n d dri v es the address b us with this v alue. the gpio ports remain as con? gure d by the user . prior to entering sleep mode, the data b us is dri v en lo w and th e control signals mreq, cs3:0, instrd, b usa ck, ioreq,rd, and w r are dri v en high. halt mode ex ecution of the cpu s hal t instruction places the ez80f92 de vice into hal t mode. in hal t mode, the operating characteristics are: caution:
ps015309-1004 preliminary low-power modes ez80f92/ez80f93 product specification 37 ? primary crystal oscillator is enabled and continues to operate ? the system clock is enabled and continues to operate ? the cpu is idle ? the program counter (pc) stops incrementing the cpu can be brought out of hal t mode by an y of the follo wing operations: ? a nonmaskable interrupt ( nmi) ? a maskable interrupt ? a reset via the e xternal reset pin dri v en lo w ? a w atch-dog t imer time-out (if con? gured to generate either an nmi or reset upon time-out) ? a reset via e x ecution of a deb ug reset command t o minimize current in hal t mode, the system clock should be disabled for all unused on-chip peripherals via the clock peripheral po wer -do wn re gisters. during hal t mode, the cpu freezes the l ast address and dri v es the address b us with this v alue. the gpio ports remain a s c on? gured by the user . prior to enter - ing hal t mode, the data b us is dri v en l o w and the control signals mreq, cs3:0, instrd, b usa ck, ioreq, rd , and wr are dri v en high. clock peripheral power-down registers t o reduce po wer , the clock peripheral po wer -do wn re gisters allo w the system clock to be disabled unused on-chip peripherals. upon reset , all peripherals are enabled. the clock to unused peripherals can be disabled by setting the appropriate bit in the clock peripheral po wer -do wn re gisters to 1. when po wered do wn, the peripherals are com - pletely disabled. t o reenable, the bit in the clock peripheral po wer -do wn re gisters must be cleared to 0. man y peripherals feature separate enable/disable control bits that must be appropriately set for operation. these peripheral speci? c enable/disable bits do not pro vide the same le v el of po wer reduction as the clock peripheral po wer -do wn re gisters. when po wered do wn, the standard peripheral control re gisters are not accessible for read or write access. see t ables 5 and 6 . caution:
ps015309-1004 preliminary low-power modes ez80f92/ez80f93 product specification 38 t able 5. clock peripheral power-down registe r (c lk_ppd1 = 00dbh ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r r/w r/w r/w r/w note: r/w = read/write; r = read only. bit position v alue description 7 gpio_d_off 1 system clock to gpio port d is powered down. port d alternate functions do not operate correctly. 0 system clock to gpio port d is powered up. 6 gpio_c_off 1 system clock to gpio port c is powered down. port c alternate functions do not operate correctly. 0 system clock to gpio port c is powered up. 5 gpio_b_off 1 system clock to gpio port b is powered down. port b alternate functions do not operate correctly. 0 system clock to gpio port b is powered up. 4 reserved. 3 spi_off 1 system clock to spi is powered down. 0 system clock to spi is powered up. 2 i2c_off 1 system clock to i 2 c is powered down. 0 system clock to i 2 c is powered up. 1 uar t1_off 1 system clock to uart1 is powered down. 0 system clock to uart1 is powered up. 0 uar t0_off 1 system clock to uart0 and irda endec is powered down. 0 system clock to uart0 and irda endec is powered up.
ps015309-1004 preliminary low-power modes ez80f92/ez80f93 product specification 39 t able 6. clock peripheral power-down register 2 (c lk_ppd2 = 00dc h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r r/w r/w r/w r/w r/w r/w note: r/w = read/write; r = read only. bit position v alue description 7 phi_off 1 phi clock output is disabled (output is high-impedance). 0 phi clock output is enabled. 6 0 reserved. 5 pr t5_off 1 system clock to prt5 is powered down. 0 system clock to prt5 is powered up. 4 pr t4_off 1 system clock to prt4 is powered down. 0 system clock to prt4 is powered up. 3 pr t3_off 1 system clock to prt3 is powered down. 0 system clock to prt3 is powered up. 2 pr t2_off 1 system clock to prt2 is powered down. 0 system clock to prt2 is powered up. 1 pr t1_off 1 system clock to prt1 is powered down. 0 system clock to prt1 is powered up. 0 pr t0_off 1 system clock to prt0 is powered down. 0 system clock to prt0 is powered up.
ps015309-1004 preliminary general-purpose input/output ez80f92/ez80f93 product specification 40 general-purpose input/output gpio overview the ez80f92 de vice features 24 general-purpose input/output (gpio) pins. the gpio pins are assembled as three 8-bit ports port b, port c, and port d. all port signals can be con? gured for use as either inputs or outputs. in addition, all of the port pins can be used as v ectored interrupt sources for the cpu. gpio operation the gpio operation is the same for all 3 gpio ports (ports b, c, and d). each port fea - tures eight gpio port pins. the operating mode for each pin is controlled by four bits that are di vided between four 8-bit re gisters. these gpio mode control re gisters are: ? port x data re gister (px_dr) ? port x data direction re gister (px_ddr) ? port x alternate re gister 1 (px_al t1) ? port x alternate re gister 2 (px_al t2) where x can be b , c , or d representing an y of the three gpio ports b, c, or d. the mode for each pin is controlled by setting each re gister bit pertinent to the pin to be con? gured. f or e xample, the operating mode for port b pin 7 (pb7), is set by the v alues contained in pb_dr[7], pb_ddr[7], pb_al t1[7], and pb_al t2[7]. the combination of the gpio control re gister bits allo ws indi vidual con? guration of each port pin for nine modes. in all modes, reading of the port x data re gister returns the sam - pled state, or le v el, of the signal on the corresponding pin. t able 7 indicates the function of each port signal based upon these four re gister bits. after a reset e v ent, all gpio port pins are con? gured as standard digital inputs, with interrupts disabled. t able 7. gpio mode selection gpio mode px_al t2 bits7:0 px_al t1 bits7:0 px_ddr bits7:0 px_dr bits7:0 port mode output 1 0 0 0 0 output 0 0 0 0 1 output 1 2 0 0 1 0 input from pin high impedance 0 0 1 1 input from pin high impedance
ps015309-1004 preliminary general-purpose input/output ez80f92/ez80f93 product specification 41 gpio mode 1 . the port pin is con? gured as a standard digital output pin. the v alue writ - ten to the port x data re gister (p x _dr) is presented on the pin. gpio mode 2 . the port pin is con? gured as a standard digital input pin. the output is tristated (high impedance). the v alue stored in the port x data re gister produces no ef fect. as in all modes, a read from the port x data re gister returns the pin s v alue. gpio mode 2 is the def ault operating mode follo wing a reset . gpio mode 3 . the port pin is con? gured as open-drain i/o. the gpio pins do not feature an internal pull-up to the supply v oltage. t o emplo y the gpio pin in open-drain mode, an e xternal pull-up resistor must connect the pin to the supply v oltage. writing a 0 to the port x data re gister outputs a lo w at the pin. writing a 1 to the port x data re gister results in high-impedance output. gpio mode 4 . the port pin is con? gured as open-source i/o. the gpio pins do not fea - ture an internal pull-do wn to the supply ground. t o emplo y the gpio pin in open- source mode, an e xternal pull-do wn resistor must connect the pin to the supply ground. writing a 1 to the port x data re gister outputs a high at the pin. writing a 0 to the port x data re gister results in a high-impedance output. gpio mode 5 . reserv ed. this pin produces high-impedance output. 3 0 1 0 0 open-drain output 0 0 1 0 1 open-drain i/o high impedance 4 0 1 1 0 open-source i/o high impedance 0 1 1 1 open-source output 1 5 1 0 0 0 reserved high impedance 6 1 0 0 1 interruptdual edge triggered high impedance 7 1 0 1 0 port b, c, or dalternate function controls port i/o. 1 0 1 1 port b, c, or dalternate function controls port i/o. 8 1 1 0 0 interruptactive low high impedance 1 1 0 1 interruptactive high high impedance 9 1 1 1 0 interruptfalling edge triggered high impedance 1 1 1 1 interruptrising edge triggered high impedance t able 7. gpio mode selection (continued) gpio mode px_al t2 bits7:0 px_al t1 bits7:0 px_ddr bits7:0 px_dr bits7:0 port mode output
ps015309-1004 preliminary general-purpose input/output ez80f92/ez80f93 product specification 42 gpio mode 6 . this bit enables a dual edge-triggered interrupt mode. both a rising and a f alling edge on the pin cause an interrupt request to be sent to the cpu. writing a 1 to the port x data re gister bit position resets the corresponding interrupt request. writing a 0 pro - duces no ef fect. the programmer must set the port x data re gister before entering the edge-triggered interrupt mode. gpio m ode 7 . f or ports b, c, and d, the port pin is con? gured to pass control o v er to the alternate (secondary) functions assigned to the pin. f or e xample, the alternate mode func - tion for pc7 is ri1 and the alternate mode function for pb4 is the t imer 4 out. when gpio mode 7 is enabled, the pin output data and pin tristated control come from the alter - nate function's data output and tristate control, respecti v ely . the v alue in the port x data re gister produces no ef fect on operation. input signals are sampled by the system clock before being passed to the alternate function input. gpio m ode 8 . the port pin is con? gured for le v el-sensiti v e interrupt modes. an interrupt request is generated when the le v el at the pin is the same as the le v el stored in the port x data re gister . the port pin v alue is sampled by the system clock. the input pin must be held at the selected interrupt le v el for a minimum of 2 clock periods to initiate an interrupt. the interrupt request remains acti v e as long as this condition is maintained at the e xternal source. gpio m ode 9 . the port pin is con? gured for single edge-triggered interrupt mode. the v alue in the port x data re gister determines if a positi v e or ne g ati v e edge causes an inter - rupt request. a 0 in the port x data re gister bit sets the selected pin to generate an interrupt request for f alling edges. a 1 in the port x data re gister bit sets the selected pin to generate an interrupt request for rising edges. the interrupt request remains acti v e until a 1 is writ - ten to the corresponding interrupt request of the port x data re gister bit. writing a 0 pro - duces no ef fect on operation. the programmer must set the port x data re gister before entering the edge-triggered interrupt mode. a simpli? ed block diagram of a gpio port pin is illustrated in figure 5 . note:
ps015309-1004 preliminary general-purpose input/output ez80f92/ez80f93 product specification 43 gpio interrupts each port pin can be used as an interrupt source. interrupts can be either le v el- or edge- triggered. level-t riggered interrupts when the port is con? gured for le v el-triggered interrupts, the corresponding port pin is tristated. an interrupt request is generated when the le v el at the pin is the same as the le v el stored in the port x data re gister . the port pin v alue is sampled by the system clock. the input pin must be held at the selected interrupt le v el for a minimum of 2 consecuti v e clock c ycles to initiate an interrupt. the interrupt request remains acti v e as long as this condition is maintained at the e xternal source. f or e xample, if pd3 is programmed for lo w-le v el interrupt and the pin is forced lo w for 2 consecuti v e clock c ycles, an interrupt request signal is generated from that port pin and sent to the cpu. the interrupt request signal remains acti v e until the e xternal de vice dri v - ing pd3 forces the pin high. edge-t riggered interrupts when the port is con? gured for edge-triggered interrupts, the corresponding port pin is tristated. if the pin recei v es the correct edge from an e xternal de vice, the port pin generates an interrupt request signal to the cpu. an y time a port pin is con? gured for edge-triggered figure 5. gpio port pin block diagram port pin gpio register data (input) gpio register data (output) system clock system clock data bus mode 1 gnd v dd mode 1 mode 3 mode 4 dq d qd q
ps015309-1004 preliminary general-purpose input/output ez80f92/ez80f93 product specification 44 interrupt, writing a 1 to that pin s port x data re gister causes a reset of the edge-detected interrupt. the programmer must set the bit in the port x data re gister to 1 before entering either single or dual edge-triggered interrupt mode for that port pin. when con? gured for dual edge-triggered interrupt mode (gpio mode 6), both a rising and a f alling edge on the pin cause an interrupt request to be sent to the cpu. when con? gured for single edge-triggered interrupt mode (gpio mode 9), the v alue in the port x data re gister determines if a positi v e or ne g ati v e edge causes an interrupt request. a 0 in the port x data re gister bit sets the selected pin to generate an interrupt request for f alling edges. a 1 in the port x data re gister bit sets the selected pin to generate an interrupt request for rising edges. gpio control registers the 12 gpio control re gisters operate in groups of four with a set for each port (b, c, and d). each gpio port features a port data re gister , port data direction re gister , port alternate re gister 1, and port alternate re gister 2. port x data registers when the port pins are con? gured for one of the output modes, the data written to the port x data re gisters, detailed in t able 8 , are dri v en on the corresponding pins. in all modes, reading from the port x data re gisters al w ays returns the current sampled v alue of the cor - responding pins. when the port pins are con? gured as edge-triggered interrupt sources, writing a 1 to the corresponding bit in the port x data re gister clears the interrupt signal that is sent to the cpu. when the port pins are con? gured for edge-selectable interrupts or le v el-sensiti v e interrupts, the v alue written to the port x data re gister bit selects the inter - rupt edge or interrupt le v el. see t able 7 for more information. t able 8. port x data register s (p b_dr = 009ah, pc_dr = 009eh, pd_dr = 00a2h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: x = undefined; r/w = read/write.
ps015309-1004 preliminary general-purpose input/output ez80f92/ez80f93 product specification 45 port x data direction registers in conjunction with the other gpio control re gisters, the port x data direction re gisters, detailed in t able 9 , control the operating modes of the gpio port pins. see t able 7 for more information. port x alternate register 1 in conjunction with the other gpio control re gisters, the port x alternate re gister 1, detailed in t able 10 , control the operating modes of the gpio port pins. see t able 7 for more information. port x alternate register 2 in conjunction with the other gpio control re gisters, the port x alternate re gister 2, detailed in t able 11 , control the operating modes of the gpio port pins. see t able 7 for more information. t able 9. port x data direction register s (p b_ddr = 009bh, pc_ddr = 009fh, pd_ddr = 00a3h ) bit 7 6 5 4 3 2 1 0 reset 1 1 1 1 1 1 1 1 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. t able 10. port x alternate registers 1 (p b_al t1 = 009ch, pc_al t1 = 00a0h, pd_al t1 = 00a4h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. t able 1 1. port x alternate registers 2 (p b_al t2 = 009dh, pc_al t2 = 00a1h, pd_al t2 = 00a5h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write.
ps015309-1004 preliminary interrupt controller ez80f92/ez80f93 product specification 46 interrupt controller the interrupt controller on the ez80f92 de vice routes the interrupt request signals from the internal peripherals and e xternal de vices (via the gpio pins) to the cpu. maskable interrupts on the ez80f92 de vice, all maskable interrupts use the cpu s v ectored interrupt function. t able 12 lists the lo w-byte v ector for each of the maskable interrupt sources. the maskable interrupt sources are listed in order of priority , with v ector 00h being the high - est-priority interrupt. the full 16-bit interrupt v ector is located at starting address {i[7:0], ivect[7:0]} where i[7:0] is the cpu s interrupt p age address re gister . the user s program should store the starting address of the interrupt service routine ( isr) in the tw o-byte interrupt v ector locations. f or e xample, for adl mode the tw o-byte address for the spi interrupt service routine w ould be stored at { 00h , i[7:0], 1eh} and { 00h , i[7:0], 1fh }. in z80 mode, the tw o-byte address for the spi interrupt service rou - t able 12. interrupt v ector sources by priority v ector source v ector source v ector source v ector source 00h unused 1ah uar t 1 34h port b 2 4eh port c 7 02h unused 1ch i 2 c 36h port b 3 50h port d 0 04h unused 1eh spi 38h port b 4 52h port d 1 06h unused 20h unused 3ah port b 5 54h port d 2 08h flash 22h unused 3ch port b 6 56h port d 3 0ah pr t 0 24h unused 3eh port b 7 58h port d 4 0ch pr t 1 26h unused 40h port c 0 5ah port d 5 0eh pr t 2 28h unused 42h port c 1 5ch port d 6 10h pr t 3 2ah unused 44h port c 2 5eh port d 7 12h pr t 4 2ch unused 46h port c 3 60h unused 14h pr t 5 2eh unused 48h port c 4 62h unused 16h r tc 30h port b 0 4ah port c 5 64h unused 18h uar t 0 32h port b 1 4ch port c 6 66h unused note: absolute locations 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h, and 66h are reserved for hardware reset, nmi, and the rst instruction.
ps015309-1004 preliminary interrupt controller ez80f92/ez80f93 product specification 47 tine w ould be stored at {mb ase[7:0], i[7:0], 1eh } and {mb ase, i[7:0], 1fh }. the least- signi? cant byte is stored at the lo wer address. when an y one or more of the interrupt requests ( irqs) become acti v e, an interrupt request is generated by the interrupt controller and sent to the cpu. the corresponding 8-bit inter - rupt v ector for the highest-priority interrupt is placed on the 8-bit interrupt v ector b us, ivect[7:0]. the interrupt v ector b us is internal to the ez80f92 de vice and is therefore not visible e xternally . the response time of the cpu to an interrupt request is a function of the current instruction being e x ecuted as well as the number of w ait states being asserted. the interrupt v ector , {i[7:0], ivect[7:0]}, is visible on the address b us, addr[15:0], when the interrupt service routine be gins. the response of the cpu to a v ectored interrupt on the ez80f92 de vice is e xplained in t able 13 . interrupt sources are required to be acti v e until the interrupt service routine starts. it is recommended that the interrupt p age address re gister (i) v alue be changed by the user from its def ault v alue of 00h as this address can create con? icts between the nonmaskable interrupt v ector , the rst instruction addresses, and the maskable interrupt v ectors. t able 13. v ectored interrupt operation memory mode adl bit madl bit operation z80 mode 0 0 read the lsb of the interrupt vector placed on the internal vectored interrupt bus, ivect [7:0], by the interrupting peripheral. ? ief1 0 ? ief2 0 ? the starting program counter is ef fectively {mbase, pc[15:0]} ? push the 2-byte return address pc[15:0] onto the ({mbase,sps}) stack ? the adl mode bit remains cleared to 0 ? the interrupt vector address is located at {mbase, i[7:0], ivect[7:0]} ? pc[15:0] ({mbase, i[7:0], ivect[7:0]}) ? the ending program counter is ef fectively {mbase, pc[15:0]} ? the interrupt service routine must end with reti adl mode 1 0 read the lsb of the interrupt vector placed on the internal vectored interrupt bus, ivect [7:0], by the interrupting peripheral. ? ief1 0 ? ief2 0 ? the starting program counter is pc[23:0] ? push the 3-byte return address, pc[23:0], onto the spl stack ? the adl mode bit remains set to 1 ? the interrupt vector address is located at {00h, i[7:0], ivect[7:0]} ? pc[15:0] ({00h, i[7:0], ivect[7:0]}) ? the ending program counter is {00h, pc[15:0]} ? the interrupt service routine must end with reti
ps015309-1004 preliminary interrupt controller ez80f92/ez80f93 product specification 48 nonmaskable interrupts an acti v e lo w input on the nmi pin generates an interrupt request to the cpu. this non - maskable interrupt is al w ays serviced by the cpu re g ardless of the state of the interrupt enable ? ags (ief1 and ief2). the nonmaskable interrupt is prioritized higher than all maskable interrupts. the response of the cpu to a nonmaskable interrupt is described in detail in the ez80 cpu user manual (um0077). z80 mode 0 1 read the lsb of the interrupt vector placed on the internal vectored interrupt bus, ivect[7:0], bus by the interrupting peripheral. ? ief1 0 ? ief2 0 ? the starting program counter is ef fectively {mbase, pc[15:0]} ? push the 2-byte return address, pc[15:0], onto the spl stack ? push a 00h byte onto the spl stack to indicate an interrupt from z80 mode (because adl = 0) ? set the adl mode bit to 1 ? the interrupt vector address is located at {00h, i[7:0], ivect[7:0]} ? pc[15:0] ({00h, i[7:0], ivect[7:0]}) ? the ending program counter is {00h, pc[15:0]} ? the interrupt service routine must end with reti.l adl mode 1 1 read the lsb of the interrupt vector placed on the internal vectored interrupt bus, ivect [7:0], by the interrupting peripheral. ? ief1 0 ? ief2 0 ? the starting program counter is pc[23:0] ? push the 3-byte return address, pc[23:0], onto the spl stack ? push a 01h byte onto the spl stack to indicate a restart from adl mode (because adl = 1) ? the adl mode bit remains set to 1 ? the interrupt vector address is located at {00h, i[7:0], ivect[7:0]} ? pc[15:0] ({00h, i[7:0], ivect[7:0]}) ? the ending program counter is {00h, pc[15:0]} ? the interrupt service routine must end with reti.l t able 13. v ectored interrupt operation (continued) memory mode adl bit madl bit operation
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 49 chip selects and w ait states the ez80f92 de vice generates four chip selects for e xternal de vices. each chip select may be programmed to access either memory space or i/o space. the memory chip selects can be indi vidually programmed on a 64 kb boundary . the i/o chip selects can each choose a 256-byte section of i/o space. in addition, each chip select may be pro - grammed for up to 7 w ait states. memory and i/o chip selects each of the chip selects can be enabled for either the memory address space or the i/o address space, b ut not both. t o select the memory address space for a particular chip select, csx_io ( cs x _ctl[4]) must be reset to 0. t o select the i/o address space for a particular chip select, csx_io must be set to 1. after reset , the def ault is for all chip selects to be con? gured for the memory address space. f or either the memory address space or the i/o address space, the indi vidual chip selects must be enabled by setting csx_en ( cs x _ctl[3]) to 1. memory chip select operation operation of each of the memory chip selects is controlled by three control re gisters. t o enable a particular memory chip select, the follo wing conditions must be met: ? the chip select is enabled by setting cs x _en to 1 ? the chip select is con? gured for memory by clearing csx_io to 0 ? the address is in the associated chip select range: cs x _lbr[7:0] addr[23:16] cs x _ubr[7:0] ? no higher priority (lo wer number) chip select meets the abo v e conditions ? a memory access instruction must be e x ecuting if all of the fore going conditions are met to generate a memory chip select, then the fol - lo wing actions occur: ? the appropriate chip select cs0 , cs1 , cs2 , or cs3 is asserted (dri v en lo w) ? mreq is asserted (dri v en lo w) ? depending upon the instruction, either rd or wr is asserted (dri v en lo w) if the upper and lo wer bounds are set to the same v alue ( cs x _ubr = cs x _lbr), then a particular chip select is v alid for a single 64 kb page.
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 50 memory chip select priority a lo wer -numbered chip select is granted priority o v er a higher -numbered chip select. f or e xample, if the address space of chip select 0 o v erlaps the chip select 1 address space, chip select 0 is acti v e. reset states on reset , chip select 0 is acti v e for all addresses, because its lo wer bound re gister resets to 00h and its upper bound re gister resets to ffh . all of the other chip select lo wer and upper bound re gisters reset to 00h . memory chip select example the use of memory chip selects is demonstrated in figure 6 . the associated control re g - ister v alues indicated in t able 14 . in this e xample, all 4 chip selects are enabled and con - ? gured for memory addresses. also, cs1 o v erlaps with cs0. because cs0 is prioritized higher than cs1, cs1 is not acti v e for much of its de? ned address space. figure 6. example: memory chip select memory location ffffffh d00000h cfffffh a00000h 9fffffh 7fffffh 800000h 000000h cs3_ubr = ffh cs3_lbr = d0h cs2_ubr = cfh cs2_lbr = a0h cs1_ubr = 9fh cs0_ubr = 7fh cs0_lbr = cs1_lbr = 00h cs3 active 3 mb address space cs2 active 3 mb address space cs1 active 2 mb address space cs0 active 8 mb address space
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 51 i/o chip select operation i/o chip selects can only be acti v e when the cpu is performing i/o instructions. because the i/o space is separate from the memory space in the ez80f92 de vice, there can ne v er be a con? ict between i/o and memory addresses. the ez80f92 de vice supports a 16-bit i/o address. the i/o chip select logic decodes the high byte of the i/o address, addr[15:8]. because the upper byte of the address b us, addr[23:16], is ignored, the i/o de vices can al w ays be accessed from within an y mem - ory mode (adl or z80). the mb ase of fset v alue used for setting the z80 memor y mode page is also al w ays ignored. f our i/o chip selects are a v ailable with the ez80f92 de vice. t o generate a particular i/o chip select, the follo wing conditions must be met: ? the chip select is enabled by setting csx_en to 1 ? the chip select is con? gured for i/o by setting csx_io to 1 ? an i/o chip select address match occursaddr[15:8] = cs x _lbr[7:0] ? no higher -priority (lo wer -number) chip select meets the abo v e conditions ? the i/o address is not within the on-chip peripheral address range 0080h?0ffh . on-chip peripheral re gisters assume priority for all addresses where: 0080h addr[15:0] 00ffh ? an i/o instruction must be e x ecuting t able 14. register v alues for memory chip select example in figure 6 chip select cs x _ctl[3] cs x _en cs x _ctl[4] cs x _io cs x _lbr cs x _ubr description cs0 1 0 00h 7fh cs0 is enabled as a memory chip select. valid addresses range from 000000hC 7fffffh. cs1 1 0 00h 9fh cs1 is enabled as a memory chip select. valid addresses range from 800000hC 9fffffh. cs2 1 0 a0h cfh cs2 is enabled as a memory chip select. valid addresses range from a00000hC cfffffh. cs3 1 0 d0h ffh cs3 is enabled as a memory chip select. valid addresses range from d00000hC ffffffh.
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 52 if all of the fore going conditions are met to generate an i/o chip select, then the follo wing actions occur: ? the appropriate chip select cs0 , cs1 , cs2 , or cs3 is asserted (dri v en lo w) ? iorq is asserted (dri v en lo w) ? depending upon the instruction, either rd or wr is asserted (dri v en lo w) wait states f or each of the chip selects, programmable w ait states can be asserted to pro vide e xter - nal de vices with additional clock c ycles to complete their read or write operations. the number of w ait states for a particular chip select is controlled by the 3-bit ? eld cs x _wait ( cs x _ctl[7:5]). the w ait states can be independently programmed to pro - vide 0 to 7 w ait states for each chip select. the w ait states idle the cpu for the speci - ? ed number of system clock c ycles. wait input signal similar to the programmable w ait states, an e xternal peripheral can dri v e the w ait input pin to force the cpu to pro vide additional clock c ycles to complete its read or write oper - ation. dri ving the w ait pin lo w stalls the cpu. the cpu resumes operation on the ? rst rising edge of the internal system clock follo wing deassertion of the w ait pin. if the w ait pin is to be dri v en by an e xternal de vice, the corresponding chip select for the de vice must be programmed to pro vide at least one w ait state. due to input sampling of the w ait input pin (sho wn in figure 7 ), one program - mable w ait state is required to allo w the e xternal peripheral suf ? cient time to assert the w ait pin. it is recommended that the corresponding chip select for the e xternal de vice be programmed to pro vide the maximum number of w ait states (se v en). figure 7. w ait input sampling block diagram caution: system clock dq wait pin ez80 cpu
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 53 an e xample of w ait state operation is illustrated in figure 8 . in this e xample, the chip select is con? gured to pro vide a single w ait state. the e xternal peripheral being accessed dri v es the w ait pin lo w to request assertion of an additional w ait state. if the w ait pin is asserted for additional system clock c ycles, w ait states are added until the w ait pin is deasserted (high). chip selects during bus request/bus acknowledge cycles when the cpu relinquishes the address b us to an e xternal peripheral in response to an e xternal b us request ( b usreq ), it dri v es the b us ackno wledge pin ( b usa ck ) lo w . the e xternal peripheral can then dri v e the address b us (and data b us). the cpu continues to generate chip select signals in response to the address on the b us. external de vices cannot access the internal re gisters of the ez80f92 de vice. figure 8. example: w ait state operation read operation t clk t w ait x addr[23:0] data[7:0] (output) csx mreq rd in instrd
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 54 bus mode controller the b us mode controller allo ws the address and data b us timing and signal formats of the ez80f92 de vice to be con? gured to connect seamlessly with e xternal ez80 ? , z80-, intel-, or motorola-compatible de vices. bus modes for each of the chip selects can be con? gured independently using the chip select bus mode control re gisters. the number of cpu system clock c ycles per b us mode state is also independently programmable. f or intel tm b us mode, multiple x ed address and data can be selected in which the lo wer byte of the address and the data byte both use the data b us, d a t a[7:0]. each of the b us modes is e xplained in more detail in the follo wing sections. ez80 bus mode chip selects con? gured for ez80 b us mode do not modify the b us signals from the cpu. the timing diagrams for e xternal memory and i/o read and write operations are sho wn in the a c characteristics section on page 228 . the def ault mode for each chip select is ez80 mode. z80 bus mode chip selects con? gured for z80 mode modify the cpu b us signals to match the z80 microprocessor address and data b us interf ace signal format and timing. during read oper - ations, the z80 b us mode emplo ys three states (t1, t2, and t3) as described in t able 15 . during write operations, z80 b us mode emplo ys 3 states (t1, t2, and t3) as described in t able 16 . t able 15. z80 bus mode read states state t1 the read cycle begins in state t1. the cpu drives the address onto the address bus and the associated chip select signal is asserted. state t2 during state t2, the rd signal is asserted. depending upon the instruction, either the mreq or iorq signal is asserted. if the external w ait pin is driven low at least one cpu system clock cycle prior to the end of state t2, additional w ait states ( t wait ) are asserted until the w ait pin is driven high. state t3 during state t3, no bus signals are altered. the data is latched by the ez80f92 device at the rising edge of the cpu system clock at the end of state t 3.
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 55 z80 b us mode read and write timing is illustrated in figures 9 and 10 . the z80 b us mode states can be con? gured for 1 to 15 cpu system clock c ycles. in the ? gures, each z80 b us mode state is tw o cpu system clock c ycles in duration. figures 9 and 10 also illustrate the assertion of 1 w ait state ( t w ait ) by the e xternal peripheral during each z80 b us mode c ycle. t able 16. z80 bus mode w rite states state t1 the write cycle begins in state t1. the cpu drives the address onto the address bus, the associated chip select signal is asserted. state t2 during state t2, the wr signal is asserted. depending upon the instruction, either the mreq or iorq signal is asserted. if the external w ait pin is driven low at least one cpu system clock cycle prior to the end of state t2, additional w ait states ( t wait ) are asserted until the w ait pin is driven high. state t3 during state t3, no bus signals are altered. figure 9. example: z80 bus mode read t iming system clock addr[23:0] data[7:0] csx mreq or iorq rd w ait t clk wr t1 t2 t3
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 56 intel? b us mode chip selects con? gured for intel tm b us mode modify the cpu b us signals to duplicate a four -state memory transfer similar to that found on intel-style microcontrollers. the b us signals and ez80f92 de vice pins are mapped as illustrated in figure 11 . in intel tm b us mode, the user can select either multiple x ed or nonmultiple x ed address and data b uses. in nonmultiple x ed operation, the address and data b uses are separate. in multiple x ed opera - tion, the lo wer byte of the address, addr[7:0], also appears on the data b us, d a t a[7:0], during state t1 of the intel tm b us mode c ycle. during multiple x ed operation, the lo wer byte of the address b us also appears on the address b us in addition to the data b us. figure 10. example: z80 bus mode w rite t iming system clock addr[23:0] data[7:0] csx mreq or iorq rd w ait t clk wr t1 t2 t3
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 57 intel tm b us mode (separate address and data buses) during read operations with separate address and data b uses, the intel tm b us mode emplo ys 4 states (t1, t2, t3, and t4) as described in t able 17 . figure 1 1. intel tm b us mode signal and pin mapping t able 17. intel tm b us mode read states (s eparate address and data buses ) state t1 the read cycle begins in state t1. the cpu drives the address onto the address bus and the associated chip select signal is asserted. the cpu drives the ale signal high at the beginning of t1. during the middle of t1, the cpu drives ale low to facilitate the latching of the address. state t2 during state t2, the cpu asserts the rd signal. depending on the instruction, either the mreq or iorq signal is asserted. ez80 bus mode signals (pins) instrd rd wr w ait mreq iorq addr[23:0] data[7:0] multiplexed bus controller addr[7:0] intel bus signal equvalents ale rd wr ready mreq iorq addr[23:0] data[7:0] bus mode controller
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 58 during write operations with separate address and data b uses, the intel tm b us mode emplo ys 4 states (t1, t2, t3, and t4) as described in t able 18 . intel tm b us mode timing is illustrated for a read operation in figure 12 and for a write operation in figure 13 . if the ready signal (e xternal w ait pin) is dri v en lo w prior to the be ginning of state t3, additional w ait states ( t w ait ) are asserted until the read y signal is dri v en high. the intel tm b us mode states can be con? gured for 2 to 15 cpu sys - tem clock c ycles. in the ? gures, each intel tm b us mode state is 2 cpu system clock c ycles in duration. figures 12 and 13 also illustrate the assertion of one w ait state ( t w ait ) by the selected peripheral. state t3 during state t3, no bus signals are altered. if the external ready ( w ait ) pin is driven low at least one cpu system clock cycle prior to the beginning of state t3, additional wait states ( t wait ) are asserted until the ready pin is driven high. state t4 the cpu latches the read data at the beginning of state t4. the cpu deasserts the rd signal and completes the intel tm b us mode cycle. t able 18. intel tm b us mode w rite states (separate address and data buses) state t1 the write cycle begins in state t1. the cpu drives the address onto the address bus, the associated chip select signal is asserted, and the data is driven onto the data bus. the cpu drives the ale signal high at the beginning of t1. during the middle of t1, the cpu drives ale low to facilitate the latching of the address. state t2 during state t2, the cpu asserts the wr signal. depending on the instruction, either the mreq or iorq signal is asserted. state t3 during state t3, no bus signals are altered. if the external ready ( w ait ) pin is driven low at least one cpu system clock cycle prior to the beginning of state t3, additional w ait states ( t wait ) are asserted until the ready pin is driven high. state t4 the cpu deasserts the wr signal at the beginning of state t4. the cpu holds the data and address buses through the end of t4. the bus cycle is completed at the end of t4. t able 17. intel tm b us mode read states (s eparate address and data buses )
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 59 figure 12. example: intel tm b us mode read t imingseparate address and data buses system clock addr[23:0] data[7:0] csx mreq or iorq rd ale t w ait wr ready t1 t2 t3 t4
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 60 figure 13. example: intel tm b us mode w rite t imingseparate address and data buses system clock addr[23:0] data[7:0] csx mreq or iorq wr ale t wait rd ready t1 t2 t3 t4
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 61 intel tm b us mode (multiplexed address and data bus) during read operations with multiple x ed address and data, the intel tm b us mode emplo ys 4 states (t1, t2, t3, and t4) as described in t able 19 . during write operations with multiple x ed address and data, the intel tm b us mode emplo ys 4 states (t1, t2, t3, and t4) as described in t able 20 . signal timing for intel tm b us mode with multiple x ed address and data is illustrated for a read operation in figure 14 and for a write operation in figure 15 . in the ? gures, each t able 19. intel tm b us mode read states (multiplexed address and data bus) state t1 the read cycle begins in state t1. the cpu drives the address onto the data bus and the associated chip select signal is asserted. the cpu drives the ale signal high at the beginning of t1. during the middle of t1, the cpu drives ale low to facilitate the latching of the address. state t2 during state t2, the cpu removes the address from the data bus and asserts the rd signal. depending upon the instruction, either the mreq or iorq signal is asserted. state t3 during state t3, no bus signals are altered. if the external ready ( w ait ) pin is driven low at least one cpu system clock cycle prior to the beginning of state t3, additional w ait states ( t wait ) are asserted until the ready pin is driven high. state t4 the cpu latches the read data at the beginning of state t4. the cpu deasserts the rd signal and completes the intel tm bus mode cycle. t able 20. intel tm b us mode w rite states (multiplexed address and data bus) state t1 the write cycle begins in state t1. the cpu drives the address onto the data bus and drives the ale signal high at the beginning of t1. during the middle of t1, the cpu drives ale low to facilitate the latching of the address. state t2 during state t2, the cpu removes the address from the data bus and drives the write data onto the data bus. the wr signal is asserted to indicate a write operation. state t3 during state t3, no bus signals are altered. if the external ready ( w ait ) pin is driven low at least one cpu system clock cycle prior to the beginning of state t3, additional wait states ( t wait ) are asserted until the ready pin is driven high. state t4 the cpu deasserts the write signal at the beginning of t4 identifying the end of the write operation. the cpu holds the data and address buses through the end of t4. the bus cycle is completed at the end of t4.
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 62 intel tm b us mode state is 2 cpu system clock c ycles in duration. figures 14 and 15 also illustrate the assertion of one w ait state ( t w ait ) by the selected peripheral. figure 14. example: intel tm bus mode read t imingmultiplexed address and data bus data[7:0] system clock addr[23:0] csx mreq or iorq rd ale t w ait wr ready t1 t2 t3 t4
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 63 figure 15. example: intel tm bus mode w rite t imingmultiplexed address and data bus system clock addr[23:0] data[7:0] csx mreq or iorq wr ale t wait rd ready t1 t2 t3 t4
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 64 motorola bus mode chip selects con? gured for motorola b us mode modify the cpu b us signals to duplicate an eight-state memory transfer similar to that found on motorola -style microcontrollers. the b us signals (and ez80f92 i/o pins) are mapped as illustrated in figure 16 . during write operations, the motorola b us mode emplo ys 8 states (s0, s1, s2, s3, s4, s5, s6, and s7) as described in t able 21 . figure 16. motorola bus mode signal and pin mapping t able 21. motorola bus mode read states state s0 the read cycle starts in state s0. the cpu drives r/ w high to identify a read cycle. state s1 entering state s1, the cpu drives a valid address on the address bus, addr[23:0]. state s2 on the rising edge of state s2, the cpu asserts as and ds . state s3 during state s3, no bus signals are altered. ez80 bus mode signals (pins) instrd rd wr w ait mreq iorq addr[23:0] data[7:0] motorola bus signal equvalents as ds r/w dtack mreq iorq addr[23:0] data[7:0] bus mode controller
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 65 the eight states for a write operation in motorola b us mode are described in t able 22 . state s4 during state s4, the cpu waits for a cycle termination signal dtack ( wait ), a peripheral signal. if the termination signal is not asserted at least one full cpu clock period prior to the rising clock edge at the end of s4, the cpu inserts wait ( t wait ) states until dtack is asserted. each wait state is a full bus mode cycle. state s5 during state s5, no bus signals are altered. state s6 during state s6, data from the external peripheral device is driven onto the data bus. state s7 on the rising edge of the clock entering state s7, the cpu latches data from the addressed peripheral device and deasserts as and ds . the peripheral device deasserts dtack at this time. t able 22. motorola bus mode w rite states state s0 the write cycle starts in s0. the cpu drives r/ w high (if a preceding write cycle leaves r/ w low). state s1 entering s1, the cpu drives a valid address on the address bus. state s2 on the rising edge of s2, the cpu asserts as and drives r/ w low. state s3 during s3, the data bus is driven out of the high-impedance state as the data to be written is placed on the bus. state s4 at the rising edge of s4, the cpu asserts ds . the cpu waits for a cycle termination signal dtack ( wait ). if the termination signal is not asserted at least one full cpu clock period prior to the rising clock edge at the end of s4, the cpu inserts wait ( t wait ) states until dtack is asserted. each wait state is a full bus mode cycle. state s5 during s5, no bus signals are altered. state s6 during s6, no bus signals are altered. state s7 upon entering s7, the cpu deasserts as and ds . as the clock rises at the end of s7, the cpu drives r/ w high. the peripheral device deasserts dtack at this time. t able 21. motorola bus mode read states (continued)
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 66 signal timing for motorola b us mode is illustrated for a read operation in figure 17 and for a write operation in figure 18 . in these tw o ? gures, each motorola b us mode state is 2 cpu system clock c ycles in duration. figure 17. example: motorola bus mode read t iming system clock addr[23:0] data[7:0] csx mreq or iorq ds as s3 dtack r/w s0 s1 s2 s4 s6 s5 s7
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 67 switching between bus modes each time the b us mode controller must switch from one b us mode to another , there is a one-c ycle cpu system clock delay . an e xtra clock c ycle is not required for repeated access in an y of the b us modes; nor is it required when the ez80f92 de vice switches to ez80 b us mode. the e xtra clock c ycles are not sho wn in the timing e xamples. due to the asynchronous nature of these b us protocols, the e xtra delay does not impact peripheral communication. figure 18. example: motorola bus mode w rite t iming system clock addr[23:0] data[7:0] csx mreq or iorq ds as s3 dtack r/w s0 s1 s2 s4 s6 s5 s7
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 68 chip select registers chip select x lower bound register f or memory chip selects, the chip select x lo wer bound re gister , detailed in t able 23 , de? nes the lo wer bound of the address range for which the corresponding memory chip select (if enabled) can be acti v e. f or i/o chip selects, this re gister de? nes the address to which addr[15:8] is compared to generate an i/o chip select. all chip select lo wer bound re gisters reset to 00h . t able 23. chip select x lower bound registe r (c s0_lbr = 00a8h, cs1_lbr = 00abh, cs2_lbr = 00aeh, cs3_lbr = 00b1h ) bit 7 6 5 4 3 2 1 0 cs0_lbr reset 0 0 0 0 0 0 0 0 cs1_lbr reset 0 0 0 0 0 0 0 0 cs2_lbr reset 0 0 0 0 0 0 0 0 cs3_lbr reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] cs x _lbr 00hC ffh for memory chip selects ( csx_io = 0) this byte specifies the lower bound of the chip select address range. the upper byte of the address bus, addr[23:16], is compared to the values contained in these registers for determining whether a memory chip select signal should be generated. for i/o chip selects ( csx_io = 1) this byte specifies the chip select address value. addr[15:8] is compared to the values contained in these registers for determining whether an i/o chip select signal should be generated.
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 69 chip select x upper bound register f or memory chip selects, the chip select x upper bound re gisters, detailed in t able 24 , de? nes the upper bound of the address range for which the corresponding chip select (if enabled) can be acti v e. f or i/o chip selects, this re gister produces no ef fect. the reset state for the chip select 0 upper bound re gister is ffh , while the reset state for the other chip select upper bound re gisters is 00h . t able 24. chip select x upper bound registe r (c s0_ubr = 00a9h, cs1_ubr = 00ach, cs2_ubr = 00afh, cs3_ubr = 00b2h ) bit 7 6 5 4 3 2 1 0 cs0_ubr reset 1 1 1 1 1 1 1 1 cs1_ubr reset 0 0 0 0 0 0 0 0 cs2_ubr reset 0 0 0 0 0 0 0 0 cs3_ubr reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] cs x _ubr 00hC ffh for memory chip selects (csx_io = 0) this byte specifies the upper bound of the chip select address range. the upper byte of the address bus, addr[23:16], is compared to the values contained in these registers for determining whether a chip select signal should be generated. for i/o chip selects (csx_io = 1) no effect.
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 70 chip select x control register the chip select x control re gister , detailed in t able 25 , enables the chip selects, speci? es the type of chip select, and sets the number of w ait states. the reset state for the chip select 0 control re gister is e8h , while the reset state for the 3 other chip select control re gisters is 00h . t able 25. chip select x control registe r (c s0_ctl = 00aah, cs1_ctl = 00adh, cs2_ctl = 00b0h, cs3_ctl = 00b3h ) bit 7 6 5 4 3 2 1 0 cs0_ctl reset 1 1 1 0 1 0 0 0 cs1_ctl reset 0 0 0 0 0 0 0 0 cs2_ctl reset 0 0 0 0 0 0 0 0 cs3_ctl reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r r r note: r/w = read/write; r = read only. bit position v alue description [7:5] cs x _wait 000 0 wait states are asserted when this chip select is active. 001 1 wait state is asserted when this chip select is active. 010 2 wait states are asserted when this chip select is active. 011 3 wait states are asserted when this chip select is active. 100 4 wait states are asserted when this chip select is active. 101 5 wait states are asserted when this chip select is active. 110 6 wait states are asserted when this chip select is active. 111 7 wait states are asserted when this chip select is active. 4 csx_io 0 chip select is configured as a memory chip select. 1 chip select is configured as an i/o chip select. 3 csx_en 0 chip select is disabled. 1 chip select is enabled. [2:0] 000 reserved.
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 71 chip select x bus mode control register + the chip select bus mode re gister , detailed in t able 26 , con? gures the chip select for ez80, z80, intel tm , or motorola b us modes. changing the b us mode allo ws the ez80f92 de vice to interf ace to peripherals based on the z80-, intel-, or motorola -style asynchronous b us interf aces. when a b us mode other than cpu is programmed for a particular chip select, the csx_w ait setting in that chip select control re gister is ignored. t able 26. chip select x bus mode control registe r (c s0_bmc = 00f0h, cs1_bmc = 00f1h, cs2_bmc = 00f2h, cs3_bmc = 00f3h ) bit 7 6 5 4 3 2 1 0 cs0_bmc reset 0 0 0 0 0 0 1 0 cs1_bmc reset 0 0 0 0 0 0 1 0 cs2_bmc reset 0 0 0 0 0 0 1 0 cs3_bmc reset 0 0 0 0 0 0 1 0 cpu access r/w r/w r/w r r/w r/w r/w r/w note: r/w = read/write; r = read only. bit position v alue description [7:6] bus_mode 00 ez80 bus mode. 01 z80 bus mode. 10 intel tm bus mode. 11 motorola bus mode. 5 ad_mux 0 separate address and data. 1 multiplexed address and dataappears on data bus data[7:0]. 4 0 reserved.
ps015309-1004 preliminary chip selects and wait states ez80f92/ez80f93 product specification 72 [3:0] bus_cycle 0000 not valid. 0001 each bus mode state is 1 cpu clock cycle in duration. 1, 2, 3 0010 each bus mode state is 2 cpu clock cycles in duration. 0011 each bus mode state is 3 cpu clock cycles in duration. 0100 each bus mode state is 4 cpu clock cycles in duration. 0101 each bus mode state is 5 cpu clock cycles in duration. 0110 each bus mode state is 6 cpu clock cycles in duration. 0111 each bus mode state is 7 cpu clock cycles in duration. 1000 each bus mode state is 8 cpu clock cycles in duration. 1001 each bus mode state is 9 cpu clock cycles in duration. 1010 each bus mode state is 10 cpu clock cycles in duration. 1011 each bus mode state is 11 cpu clock cycles in duration. 1100 each bus mode state is 12 cpu clock cycles in duration. 1101 each bus mode state is 13 cpu clock cycles in duration. 1110 each bus mode state is 14 cpu clock cycles in duration. 1111 each bus mode state is 15 cpu clock cycles in duration. notes: 1. setting bus_cycle to 1 in intel tm b us mode causes the ale pin to not function properly . 2. use of the external w ait input pin in z80 mode requires that bus_cycle is set to a value greater than 1. 3. bus_cycle produces no ef fect in ez80 mode. bit position v alue description
ps015309-1004 preliminary watch-dog timer ez80f92/ez80f93 product specification 73 w atch-dog timer watch-dog timer overview the w atch-dog t imer ( wdt) helps protect ag ainst corrupt or unreliable softw are, po wer f aults, and other system-le v el problems which may place the cpu into unsuitable operat - ing states. the ez80f92 wdt features: ? f our programmable time-out periods: 2 18 , 2 22 , 2 25 , and 2 27 clock c ycles ? t w o selectable wdt clock sources: the system clock or the real-t ime clock source (on-chip 32 khz crystal oscillator or 50/60 hz signal) ? a selectable time-out response: a time-out can be con? gured to generate either a reset or a nonmaskable interrupt ( nmi) ? a wdt time-out reset indicator ? ag figure 19 illustrates the block diagram for the w atch-dog t imer . figure 19. w atch-dog t imer block diagram reset nmi to ez80 cpu 28-bit upcounter control register/ reset register wdt control logic data[7:0] wdt_clk system clock rtc clock time-out compare logic (wdt_period)
ps015309-1004 preliminary watch-dog timer ez80f92/ez80f93 product specification 74 watch-dog timer operation enabling and disabling the wdt the w atch-dog t imer is disabled upon a reset . t o enable the wdt , the application pro - gram must set the wdt_en bit (bit 7) of the wdt_ctl re gister . when enabled, the wdt cannot be disabled without a reset . t ime-out period selection there are four choices of time-out periods for the wdt2 18 , 2 22 , 2 25 , and 2 27 system clock c ycles. the wdt time-out period is de? ned by the wdt_period ? eld of the wdt_ctl re gister (wdt_ctl[1:0]). the approximate time-out periods for tw o dif fer - ent wdt clock sources is listed in t able 27 . reset or nmi generation upon a wdt time-out, the rst_flag bit in the wdt_ctl re gister is set to 1. in addi - tion, the wdt can cause a reset or send a nonmaskable interrupt (nmi) signal to the cpu. the def ault operation is for the wdt to cause a reset . it asserts/deasserts on the rising edge of the clock. the rst_flag bit can be polled by the cpu to determine the source of the reset e v ent. t able 27. w atch-dog t imer approximate t ime-out delays clock source divider v alue t ime out delay 32.768 khz crystal oscillator 2 18 8.00 s 32.768 khz crystal oscillator 2 22 128 s 32.768 khz crystal oscillator 2 25 1024 s 32.768 khz crystal oscillator 2 27 4096 s 20 mhz system clock 2 18 13.1 ms* 20 mhz system clock 2 22 209.7 ms* 20 mhz system clock 2 25 1.68 s 20 mhz system clock 2 27 6.71 s 50 mhz system clock 2 18 5.2 ms 50 mhz system clock 2 22 83.9 ms 50 mhz system clock 2 25 0.67 s 50 mhz system clock 2 27 2.68 s note: * wdt time-out values should be sufficiently long to allow flash operations to complete.
ps015309-1004 preliminary watch-dog timer ez80f92/ez80f93 product specification 75 if the nmi_out bit in the wdt_ctl re gister is set to 1, then upon time-out, the wdt asserts an nmi for cpu processing. the nmi_flag bit can be polled by the cpu to determine the source of the nmi e v ent. watch-dog timer registers w atch-dog t imer control register the w atch-dog t imer control re gister , detailed in t able 28 , is an 8-bit read/write re gis - ter used to enable the w atch-dog t imer , set the time-out period, indicate the source of the most recent reset , and select the required operation upon wdt time-out. t able 28. w atch-dog t imer control register (wdt_ctl = 0093h) bit 7 6 5 4 3 2 1 0 reset 0 0 0/1 0 0 0 0 0 cpu access r/w r/w r r/w r/w r r/w r/w note: r = read only; r/w = read/write. bit position v alue description 7 wdt_en 0 wdt is disabled. 1 wd t is enabled. when enabled, the wdt cannot be disabled without a reset . 6 nmi_out 0 wdt time-out resets the cpu. 1 wdt time-out generates a nonmaskable interrupt (nmi) to the cpu. 5 rst_flag* 0 reset caused by external full-chip reset or zdi reset. 1 reset caused by wdt time-out. this flag is set by the wdt time-out, even if the nmi_out flag is set to 1. the cpu can poll this bit to determine the source of the reset or nmi. [4:3] wdt_clk 00 wdt clock source is system clock. 01 wdt clock source is real-time clock source (32 khz on-chip oscillator or 50/60hz input as set by rtc_ctrl[4]). 10 reserved . 11 reserved . 2 0 reserved. note: *rst_flag is only cleared by a non- wdt reset.
ps015309-1004 preliminary watch-dog timer ez80f92/ez80f93 product specification 76 w atch-dog t imer reset register the w atch-dog t imer reset re gister , detailed in t able 29 , is an 8-bit write only re gister . the w atch-dog t imer is reset when an a5h v alue follo wed by 5ah is written to this re gis - ter . an y amount of time can occur between the writing of the a5h v alue and the 5ah v alue, so long as the wdt time-out does not occur prior to completion. [1:0] wdt_period 00 wdt time-out period is 2 27 clock cycles. 01 wdt time-out period is 2 25 clock cycles. 10 wdt time-out period is 2 22 clock cycles. 11 wdt time-out period is 2 18 clock cycles. t able 29. w atch-dog t imer reset register (wdt_rr = 0094h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: x = undefined; w = write only. bit position v alue description [7:0] wdt_rr a5h the first write value required to reset the wdt prior to a time- out. 5ah the second write value required to reset the wdt prior to a time-out. if an a5h, 5ah sequence is written to wdt_rr, the wdt timer is reset to its initial count value, and counting resumes. bit position v alue description note: *rst_flag is only cleared by a non- wdt reset.
ps015309-1004 preliminary programmable reload timers ez80f92/ez80f93 product specification 77 programmable reload t imers programmable reload timers overview the ez80f92 de vice features six programmable reload t imers (pr t). each pr t contains a 16-bit do wncounter and a 16-bit reload re gister . in addition, each pr t features a clock di vider w ith four selectable taps for clk 4, clk 16, clk 64, and clk 256. each timer can be indi vidually enabled to operate in either single pass or continu - ous mode. the timer can be programmed to start, stop, restart from the current v alue, or restart from the initial v alue, and generate interrupts to the cpu. f our of the programmable reload t imers (timers 0C3) feature a selectable clock source input. the input for these timers can be either the system clock or the real-t ime clock ( r tc) source. t imers 0C3 can also be used for e v ent counting, with their inputs recei v ed from a gpio port pin. output from timers 4 and 5 can be directed to a gpio port pin. each of the six pr ts a v ailable on the ez80f92 de vice can be controlled indi vidually . the y do not share the same counters, reload re gisters, control re gisters, or interrupt signals. a simpli? ed block diagram of a programmable reload timer is illustrated in figure 20 . figure 20. programmable reload t imer block diagram reload registers {tmrx_rr_h, tmrx_rr_l} data[7:0] data[7:0] data[7:0] tout_en (timers 4C5 only) 16-bit down counter adjustable clock prescaler tmrx_in (timers 0C3 only) tmrx_ctl[3:2] system clock rtc source gpio pin control register tmrx_ctl prt control logic irq to ez80 cpu timer out data registers {tmrx_dr_h, tmrx_dr_l} 2 2
ps015309-1004 preliminary programmable reload timers ez80f92/ez80f93 product specification 78 programmable reload timer operation setting t imer duration there are three f actors to consider when determining programmable reload t imer dura - tionclock frequenc y , clock di vider ratio, and initial count v alue. minimum duration of the timer is achie v ed by loading 0001h . maximum duration is achie v ed by loading 0000h , because the timer ? rst rolls o v er to ffffh and then continues counting do wn to 0000h . the time-out period of the pr t is returned by the follo wing equation: t o calculate the time-out period with the abo v e equation when using an initial v alue of 0000h , enter a reload v alue of 65536 ( ffffh + 1). minimum time-out duration is 4 times longer than the input clock period and is generated by setting the clock di vider ratio to 1:4 and the reload v alue to 0001h . maximum time-out duration is 2 24 (16,777,216) times longer than the input clock period and is generated by setting the clock di vider ratio to 1:256 and the reload v alue to 0000h . single pass mode in single pass mode, when the end-of-count v alue, 0000h , is reached, counting halts, the timer is disabled, and the prt_en bit resets to 0. t o r estart the timer , the cpu must reenable the timer by setting the prt_en b it to 1 in the t imer control re gister . t o set the do wncounter to the v alue in the reload re gisters, the rst_en bit must be set to 1 in the t imer control re gister . an e xample of a pr t operating in single pass mode is illus - trated in figure 21 . t imer re gister information is indicated in t able 30 . prt time-out period = clock divider ratio x reload v alue system clock frequency
ps015309-1004 preliminary programmable reload timers ez80f92/ez80f93 product specification 79 continuous mode in continuous mode, when the end-of-count v alue, 0000h , is reached, the timer auto - matically reloads the 16-bit start v alue from the t imer reload re gisters, tmrx_rr_h and tmrx_rr_l. do wncounting continues on the ne xt clock edge. in continuous mode, the pr t continues to count until disabled. an e xample of a pr t operating in continu - ous mode is illustrated in figure 31 . t imer re gister information is indicated in t able 32 . figure 21. prt single pass mode operation example t able 30. prt single pass mode operation example parameter control register(s) v alue prt enabled tmrx_ctl[0] 1 reload and restart enabled tmrx_ctl[1] 1 prt clock divider = 4 tmrx_ctl[3:2] 00b single pass mode tmrx_ctl[4] 0 prt interrupt enabled tmrx_ctl[6] 1 prt reload value {tmrx_rr_h, tmrx_rr_l} 0004h clk clken iowrn t [7:0] irq 0 00 43 2 1 cnth t [7:0] cntl
ps015309-1004 preliminary programmable reload timers ez80f92/ez80f93 product specification 80 reading the current count v alue the cpu is capable of reading the current count v alue while the timer is running. this read e v ent does not af fect timer operation. the high byte of the current count v alue is latched during a read of the lo w byte. t imer interrupts the timer interrupt ? ag, prt_irq , is set to 1 whene v er the timer reaches its end-of-count v alue, 0000h , in single pass mode, or when the timer reloads the start v alue in con - tinuous mode. the interrupt ? ag is only set when the timer reaches 0000h (or reloads) from 0001h . the timer interrupt ? ag is not set to 1 when the timer is loaded with the v alue 0000h , which selects the maximum time-out period. the cpu can be programmed to poll the prt_irq bit for the time-out e v ent. alterna - ti v ely , an interrupt service request signal can be sent to the cpu by setting irq_en to 1. t able 31. prt continuous mode operation example t able 32. prt continuous mode operation example parameter control register(s) v alue prt enabled tmrx_ctl[0] 1 reload and restart enabled tmrx_ctl[1] 1 prt clock divider = 4 tmrx_ctl[3:2] 00b continuous mode tmrx_ctl[4] 1 prt interrupt enabled tmrx_ctl[6] 1 prt reload value {tmrx_rr_h, tmrx_rr_l} 0004h clk prt clock (clock 4) iowrn prt count value interrupt request i/o write to tmrx_ctl enables prt x4321 43
ps015309-1004 preliminary programmable reload timers ez80f92/ez80f93 product specification 81 then, when the end-of-count v alue, 0000h , is reached and prt_irq is set to 1, an inter - rupt service request signal is passed to the cpu. prt_irq is cleared to 0 and the interrupt service request signal is inacti v ated whene v er the cpu reads from the timer control re gis - ters, tmrx_ctl. t imer input source selection t imers 0C3 feature programmable input source selection. by def ault, the input is tak en from the ez80f92 de vice s system clock. alternati v ely , t imers 0C3 can tak e their input from port input pins pb0 (t imers 0 and 2) or pb1 (t imers 1 and 3). t imers 0C3 can also use the real-t ime clock source (50, 60, or 32768hz) as their clock sources. when the timer clock source is the real-t ime clock signal, the timer decrements on the second ris - ing edge of the system clock follo wing the f alling edge of the r tc_x out pin. the input source for these timers is set using the t imer input source select re gister . event counter when t imers 0C3 are con? gured to tak e their inputs from port input pins pb0 and pb1, the y function as e v ent counters. f or e v ent counting, the clock di vider i s bypassed. the pr t counters decrement on e v ery rising edge of the port pin. the port pins must be con - ? gured as inputs. due to the input sampling on the pins, the e v ent input signal frequenc y is limited to one-half the system clock frequenc y . input sampling on the port pins results in the pr t counter being updated on the ? fth rising edge of the system clock after the rising edge occurs at the port pin. t imer output t w o of the programmable reload t imers (t imers 4 and 5) can be directed to gpio port b output pins (pb4 and pb5, respecti v ely). t o enable the t imer out feature, the gpio port pin must be con? gured for alternate functions. after reset, the t imer output feature is dis - abled by def ault. the gpio output pin toggles each time the pr t reaches its end-of-count v alue. in continuous mode operation, the disabling of the t imer output feature results in a t imer output signal period that is twice the pr t time-out period. examples of the t imer output operation are illustrated in figure 22 and t able 33 . in these e xamples, the gpio output is assumed to be lo w (0) when the t imer output function is enabled.
ps015309-1004 preliminary programmable reload timers ez80f92/ez80f93 product specification 82 programmable reload timer registers each programmable reload timer is controlled using ? v e 8-bit re gisters. these re gisters are the t imer c ontrol re gister , t imer r eload lo w byte re gister , t imer r eload high byte re g - ister , t imer d ata lo w byte re gister , and t imer d ata high byte re gister . the t imer control re gister can be read or written to. the timer reload re gisters are write only and are located at the same i/o address as the timer data re gisters, which are read only . t imer control register the t imer c ontrol re gister , detailed in t able 34 , is used to control operation of the timer , including enabling the timer , selecting the clock di vider , enabling the interrupt, selecting between continuous and single pass modes, and enabling the auto-reload fea - ture. figure 22. prt t imer output operation example t able 33. prt t imer out operation example parameter control register(s) v alue prt enabled tmrx_ctl[0] 1 reload and restart enabled tmrx_ctl[1] 1 prt clock divider = 4 tmrx_ctl[3:2] 00b continuous mode tmrx_ctl[4] 1 prt reload value {tmrx_rr_h, tmrx_rr_l} 0003h clk prt clock (clock 4) iowrn prt count value timer output i/o write to tmrx_ctl enables prt x3 213 21
ps015309-1004 preliminary programmable reload timers ez80f92/ez80f93 product specification 83 t able 34. t imer control registe r (t mr0_ctl = 0080h, tmr1_ctl = 0083h, tmr2_ctl = 0086h , t mr3_ctl = 0089h, tmr4_ctl = 008ch, or tmr5_ctl = 008fh ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r/w r/w r/w r/w r/w r/w r/w note: r = read only; r/w = read/write. bit position v alue description 7 prt_irq 0 the timer does not reach its end-of-count value. this bit is reset to 0 every time the tmrx_ctl register is read. 1 the timer reaches its end-of-count value. if irq_en is set to 1, an interrupt signal is sent to the cpu. this bit remains 1 until the tmrx_ctl register is read. 6 irq_en 0 timer interrupt requests are disabled. 1 timer interrupt requests are enabled. 5 0 reserved. 4 prt_mode 0 the timer operates in single pass mode. prt_en (bit 0) is reset to 0, and counting stops when the end-of-count value is reached. 1 the timer operates in continuous mode. the timer reload value is written to the counter when the end-of-count value is reached. [3:2] clk_div 00 clock 4 is the timer input source. 01 clock 16 is the timer input source. 10 clock 64 is the timer input source. 11 clock 256 is the timer input source. 1 rst_en 0 the r eload and restart function is disabled. 1 the reload and restart function is enabled. when a 1 is written to this bit, the values in the reload registers are loaded into the downcounter when the timer restarts. the programmer must ensure that this bit is set to 1 each time single-pass mode is used. 0 prt_en 0 the programmable reload timer is disabled. 1 the programmable reload timer is enabled.
ps015309-1004 preliminary programmable reload timers ez80f92/ez80f93 product specification 84 t imer data registerlow byte this read only re gister returns the lo w byte of the current count v alue of the selected timer . the t imer data re gisterlo w byte, detailed in t able 35 , can be read while the timer is in operation. reading the current count v alue does not af fect timer operation. t o read the 16-bit data of the current count v alue, {tmrx_dr_h[7:0], tmrx_dr_l[7:0]}, ? rst read the t imer data re gisterlo w byte and then read the t imer data re gister high byte. the t imer data re gisterhigh byte v alue is latched when a read of the t imer data re gisterlo w byte occurs. the t imer data re gisters and t imer reload re gisters share the same address space. t imer data registerhigh byte this read only re gister returns the high byte of the current count v alue of the selected timer . the t imer data re gisterhigh byte, detailed in t able 36 , can be read while the timer is in operation. reading the current count v alue does not af fect timer operation. t o read the 16-bit data of the current count v alue, {tmrx_dr_h[7:0], tmrx_dr_l[7:0]}, ? rst read the t imer data re gisterlo w byte and then read the t imer data re gister high byte. the t imer data re gisterhigh byte v alue is latched when a read of the t imer data re gisterlo w byte occurs. the timer data re gisters and timer reload re gisters share the same address space. t able 35. t imer data registerlow byt e (t mr0_dr_l = 0081h, tmr1_dr_l = 0084h, tmr2_dr_l = 0087h , t mr3_dr_l = 008ah, tmr4_dr_l = 008dh, or tmr5_dr_l = 0090h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] tmr x _dr_l 00hCffh these bits represent the low byte of the 2-byte timer data value, {tmrx_dr_h[7:0], tmrx_dr_l[7:0]}. bit 7 is bit 7 of the 16-bit timer data value. bit 0 is bit 0 ( lsb) of the 16- bit timer data value. note: note:
ps015309-1004 preliminary programmable reload timers ez80f92/ez80f93 product specification 85 t imer reload registerlow byte the t imer reload re gisterlo w byte, detailed in t able 37 , stores the least-signi? cant byte ( lsb) of the 2-byte timer reload v alue. in continuous mode, the timer reload v alue is reloaded into the timer upon end-of-count. when rst_en (tmrx_ctl[1]) is set to 1 to enable the automatic reload and restart function, the timer reload v alue is written to the timer on the ne xt rising edge of the clock. the t imer data re gisters and t imer reload re gisters share the same address space. t able 36. t imer data registerhigh byt e (t mr0_dr_h = 0082h, tmr1_dr_h = 0085h, tmr2_dr_h = 0088h , t mr3_dr_h = 008bh, tmr4_dr_h = 008eh, or tmr5_dr_h = 0091h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] tmr x _dr_h 00hCffh these bits represent the high byte of the 2-byte timer data value, {tmrx_dr_h[7:0], tmrx_dr_l[7:0]}. bit 7 is bit 15 ( msb) of the 16-bit timer data value. bit 0 is bit 8 of the 16-bit timer data value. t able 37. t imer reload registerlow byt e (t mr0_rr_l = 0081h, tmr1_rr_l = 0084h, tmr2_rr_l = 0087h , t mr3_rr_l = 008ah, tmr4_rr_l = 008dh, or tmr5_rr_l = 0090h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write only. bit position v alue description [7:0] tmr x _rr_l 00hCffh these bits represent the low byte of the 2-byte timer reload value, {tmrx_rr_h[7:0], tmrx_rr_l[7:0]}. bit 7 is bit 7 of the 16-bit timer reload value. bit 0 is bit 0 ( lsb) of the 16-bit timer reload value. note:
ps015309-1004 preliminary programmable reload timers ez80f92/ez80f93 product specification 86 t imer reload registerhigh byte the t imer reload re gisterhigh byte, detailed in t able 38 , stores the most-signi? cant byte ( msb) of the 2-byte timer reload v alue. in continuous mode, the timer reload v alue is reloaded into the timer upon end-of-count. when rst_en (tmrx_ctl[1]) is set to 1 to enable the automatic reload and restart function, the timer reload v alue is written to the timer on the ne xt rising edge of the clock. the t imer data re gisters and t imer reload re gisters share the same address space. t imer input source select register the t imer input source select re gister , detailed in t able 39 , sets the input source for pro - grammable reload t imer 0C3 (tmr0, tmr1, tmr2, tmr3). ev ent frequenc y must be less than one-half of the system clock frequenc y . when con? gured for e v ent inputs through the port pins, the t imers decrement on the ? fth system clock rising edge follo w - ing the rising edge of the port pin. the timer e v ent input can arri v e from the gpio port, the real-time clock, or the system clock. the v alue of the clock di vider in the t imer control re gister is ignored when the timer e v ent input is either from the gpio port pin or the real- time clock source. t able 38. t imer reload registerhigh byt e (t mr0_rr_h = 0082h, tmr1_rr_h = 0085h, tmr2_rr_h = 0088h , t mr3_rr_h = 008bh, tmr4_rr_h = 008eh, or tmr5_rr_h = 0091h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write only. bit position v alue description [7:0] tmr x _rr_h 00hCffh these bits represent the high byte of the 2-byte timer reload value, {tmrx_rr_h[7:0], tmrx_rr_l[7:0]}. bit 7 is bit 15 ( msb) of the 16-bit timer reload value. bit 0 is bit 8 of the 16-bit timer reload value. note:
ps015309-1004 preliminary programmable reload timers ez80f92/ez80f93 product specification 87 t able 39. t imer input source select registe r (t mr_iss = 0092h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:6] tmr3_in 00 the timer counts at the system clock divided by the clock divider. 01 the timer event input is the real-time clock source (32 khz or 50/60 hzrefer to the real-t ime clock section on page 88 for details). 10 the timer event input source i s the gpio port b pin 1. 11 the timer event input source i s the gpio port b pin 1. [5:4] tmr2_in 00 the timer counts at the system clock divided by the clock divider. 01 the timer event input is the real-time clock source (32 khz or 50/60 hzrefer to the real-t ime clock section on page 88 for details). 10 the timer event input is the gpio port b pin 0. 11 the timer event input is the gpio port b pin 0. [3:2] tmr1_in 00 the timer counts at the system clock divided by the clock divider. 01 the timer event input is the real-time clock source (32 khz or 50/60 hzrefer to the real-t ime clock section on page 88 for details). 10 the timer event input is the gpio port b pin 1. 11 the timer event input is the gpio port b pin 1. [1:0] tmr0_in 00 timer counts at system clock divided by clock divider. 01 timer event input is real-time clock source (32 khz or 50/60 hzrefer to the real-t ime clock section on page 88 for details). 10 the timer event input is the gpio port b pin 0. 11 the timer event input is the gpio port b pin 0.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 88 real-t ime clock real-time clock overview the real-t ime clock ( r tc) k eeps time by maintaining a count of seconds, minutes, hours, day-of-the-week, day-of-the-month, year , and century . the current time is k ept in 24-hour format. the format for all count and alarm re gisters is selectable between binary and binary-coded-decimal ( bcd). the calendar operation maintains the correct day of the month and automatically compensates for leap year . a simpli? ed block diagram of the r tc and the associated on-chip, lo w-po wer , 32 khz oscillator is illustrated in figure 23 . connections to an e xternal battery supply and 32 khz crystal netw ork are also demon - strated in figure 23 . figure 23. real-t ime clock and 32khz oscillator block diagram rtc_v rtc_x dd v enab le clk_sel (rtc_ctrl[4]) 32 kh z crystal battery irq addr[15:0] data[7:0] rtc clock system clock dd v dd in c low-power 32 khz oscillator real-time clock to ez80 cpu rtc_x out c r1
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 89 real-time clock alarm the clock can be programmed to generate an alarm condition when the current count matches the alarm set-point re gisters. alarm re gisters are a v ailable for seconds, minutes, hours, and day-of-the-week. each alarm can be independently enabled. t o generate an alarm condition, the current time must match all enabled alarm v alues. f or e xample, if the day-of-the-week and hour alarms are both enabled, the alarm only occurs at the speci? ed hour on the speci? ed day . the alarm triggers an interrupt if the interrupt enable bit, int_en, is set. the alarm ? ag, alarm, and corresponding interrupt to the cpu are cleared by reading the r tc_ctrl re gister . alarm v alue re gisters and alarm control re gisters can be written at an y time. alarm condi - tions are generated when the count v alue matches the alarm v alue. the comparison of alarm and count v alues occurs whene v er the r tc count increments (one time e v ery sec - ond). the r tc can also be forced to perform a comparison at an y time by writing a 0 to the r tc_unlock bit (r tc_unlock is not required to be changed to a 1 ? rst). real-time clock oscillator and source selection the r tc count is driven by either an external 32 khz on-chip oscillator or a 50/60 hz power -line frequency input connected to the 32 khz r tc_x out pin. a n internal di vider compensates for each of these options. the clock source and po wer -line frequencies are selected in the r tc_ctrl re gister . writing to the r tc_ctrl re gister resets the clock di vider . real-time clock battery backup the po wer supply pin (r tc_v dd ) for the real-t ime clock and associated lo w-po wer 32 khz oscillator is isolated from the other po wer supply pins on the ez80f92 de vice. t o ensure that the r tc continues to k eep time in the e v ent of loss of line po wer to the appli - cation, a battery can be used to supply po wer to the r tc and the oscillator via the r tc_v dd pin. all v ss (ground) pins should be connected together on the printed circuit assembly . real-time clock recommended operation f ollo wing a reset from a po wered-do wn condition, the counter v alues of the r tc are unde? ned and all alarms are disabled. after a reset from a po wered-do wn condition, the follo wing procedure is recommended: ? write to r tc_ctrl to set r tc_unlock and clk_sel ? write v alues to the r tc count re gisters to set the current time ? write v alues to the r tc alarm re gisters to set the appropriate alarm conditions
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 90 ? write to r tc_ctrl to clear the r tc_unlock bit; clearing the r tc_unlock bit resets and enables the clock di vider real-time clock registers the real-t ime clock re gisters are accessed via the address and data b us using i/o instruc - tions. r tc_unlock controls access to the r tc count re gisters. when unlock ed (r tc_unlock = 1), the r tc count is disabled and the count re gisters are read/write. when lock ed (r tc_unlock = 0), the r tc count is enabled and the count re gisters are read only . the def ault, at reset , is for the r tc to be lock ed. real-t ime clock seconds register this re gister contains the current seconds count. the v alue in the r tc_sec re gister is unchanged by a reset . the current setting of bcd_en determines whether the v alues in this re gister are binary (bcd_en = 0) or binary-coded decimal (bcd_en = 1). access to this re gister is read only if the r tc is lock ed and read/write if the r tc is unlock ed. see t able 40 . t able 40. real-t ime clock seconds registe r (r tc_sec = 00e0h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] ten_sec 0C5 the tens digit of the current seconds count. [3:0] sec 0C9 the ones digit of the current seconds count. binary operation (bcd_en = 0) bit position v alue description [7:0] sec 00hC 3bh the current seconds count.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 91 real-t ime clock minutes register this re gister contains the current minutes count. see t able 41 . t able 41. real-t ime clock minutes registe r (r tc_min = 00e1h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] ten_min 0C5 the tens digit of the current minutes count. [3:0] min 0C9 the ones digit of the current minutes count. binary operation (bcd_en = 0) bit position v alue description [7:0] min 00hC 3bh the current minutes count.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 92 real-t ime clock hours register this re gister contains the current hours count. see t able 42 . t able 42. real-t ime clock hours registe r (r tc_hrs = 00e2h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] ten_hrs 0C2 the tens digit of the current hours count. [3:0] hrs 0C9 the ones digit of the current hours count. binary operation (bcd_en = 0) bit position v alue description [7:0] hrs 00hC 17h the current hours count.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 93 real-t ime clock day-of-the-w eek register this re gister contains the current day-of-the-week count. the r tc_do w re gister be gins counting at 01h . see t able 43 . t able 43. real-t ime clock day-of-the-w eek registe r (r tc_dow = 00e3h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 x x x x cpu access r r r r r/w* r/w* r/w* r/w* note: x = unchanged by reset; r = read only; r/w* = read only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] 0000 reserved. [3:0] dow 1-7 the current day-of-the-week.count. binary operation (bcd_en = 0) bit position v alue description [7:4] 0000 reserved. [3:0] dow 01hC 07h the current day-of-the-week count.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 94 real-t ime clock day-of-the-month register this re gister contains the current day-of-the-month count. the r tc_dom re gister be gins counting at 01h . see t able 44 . t able 44. real-t ime clock day-of-the-month registe r (r tc_dom = 00e4h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] tens_dom 0C3 the tens digit of the current day-of-the-month count. [3:0] dom 0C9 the ones digit of the current day-of-the-month count. binary operation (bcd_en = 0) bit position v alue description [7:0] dom 01hC 1fh the current day-of-the-month count.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 95 real-t ime clock month register this re gister contains the current month count. see t able 45 . t able 45. real-t ime clock month registe r (r tc_mon = 00e5h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] tens_mon 0C1 the tens digit of the current month count. [3:0] mon 0C9 the ones digit of the current month count. binary operation (bcd_en = 0) bit position v alue description [7:0] mon 01hC 0ch the current month count.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 96 real-t ime clock y ear register this re gister contains the current year count. see t able 46 . t able 46. real-t ime clock y ear registe r (r tc_yr = 00e6h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] tens_yr 0C9 the tens digit of the current year count. [3:0] yr 0C9 the ones digit of the current year count. binary operation (bcd_en = 0) bit position v alue description [7:0] yr 00hC 63h the current year count.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 97 real-t ime clock century register this re gister contains the current century count. see t able 47 . t able 47. real-t ime clock century registe r (r tc_cen = 00e7h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: x = unchanged by reset; r/w* = read only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] tens_cen 0C9 the tens digit of the current century count. [3:0] cen 0C9 the ones digit of the current century count. binary operation (bcd_en = 0) bit position v alue description [7:0] cen 00hC 63h the current century count.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 98 real-t ime clock alarm seconds register this re gister contains the alarm seconds v alue. see t able 48 . t able 48. real-t ime clock alarm seconds registe r (r tc_asec = 00e8h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: x = unchanged by reset; r/w = read/write. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] a ten_sec 0C5 the tens digit of the alarm seconds value. [3:0] asec 0C9 the ones digit of the alarm seconds value. binary operation (bcd_en = 0) bit position v alue description [7:0] asec 00hC 3bh the alarm seconds value.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 99 real-t ime clock alarm minutes register this re gister contains the alarm minutes v alue. see t able 49 . t able 49. real-t ime clock alarm minutes registe r (r tc_amin = 00e9h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: x = unchanged by reset; r/w = read/write. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] a ten_min 0C5 the tens digit of the alarm minutes value. [3:0] amin 0C9 the ones digit of the alarm minutes value. binary operation (bcd_en = 0) bit position v alue description [7:0] amin 00hC 3bh the alarm minutes value.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 100 real-t ime clock alarm hours register this re gister contains the alarm hours v alue. see t able 50 . t able 50. real-t ime clock alarm hours registe r (r tc_ahrs = 00eah ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: x = unchanged by reset; r/w = read/write. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] a ten_hrs 0C2 the tens digit of the alarm hours value. [3:0] ahrs 0C9 the ones digit of the alarm hours value. binary operation (bcd_en = 0) bit position v alue description [7:0] ahrs 00hC 17h the alarm hours value.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 101 real-t ime clock alarm day-of-the-w eek register this re gister contains the alarm day-of-the-week v alue. see t able 51 . t able 51. real-t ime clock alarm day-of-the-w eek registe r (r tc_adow = 00ebh ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 x x x x cpu access r r r r r/w* r/w* r/w* r/w* note: x = unchanged by reset; r = read only; r/w* = read only if rtc locked, read/write if rtc unlocked. binary-coded-decimal operation (bcd_en = 1) bit position v alue description [7:4] 0000 reserved. [3:0] adow 1-7 the alarm day-of-the-week.value. binary operation (bcd_en = 0) bit position v alue description [7:4] 0000 reserved. [3:0] adow 01hC 07h the alarm day-of-the-week value.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 102 real-t ime clock alarm control register this re gister contains alarm enable bits for the real-t ime clock. the r tc_a ctrl re gis - ter is cleared by a reset . see t able 52 . real-t ime clock control register this re gister contains control and status bits for the real-t ime clock. some bits in the r tc_ctrl re gister are cleared by a reset . the alarm ? ag and associated interrupt (if int_en is enabled) are cleared by reading this re gister . the alarm ? ag is updated by clearing (locking) the r tc_unlock bit or by an increment of the r tc count. writ - ing to the r tc_ctrl re gister also resets the r tc clock di vider a llo wing the r tc to be synchronized to another time source. slp_w ake indicates if an r tc alarm condition initiated the cpu reco v ery from sleep mode. this bit can be check ed after reset to determine if a sleep-mode reco v ery is caused by the r tc. slp_w ake is cleared by a read of the r tc_ctrl re gister . setting bcd_en causes the r tc to use bcd counting in all re gisters including the alarm set points. clk_sel and freq_sel select the r tc clock source. if the 32 khz crystal option is selected the oscillator is enabled and the internal clock di vider i s set to di vide by 32768. if t able 52. real-t ime clock alarm control registe r (r tc_actrl = 00ech ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r/w r/w r/w r/w note: x = unchanged by reset; r/w = read/write; r = read only. bit position v alue description [7:4] 0000 reserved. 3 adow_en 0 the day-of-the-week alarm is disabled. 1 the day-of-the-week alarm is enabled. 2 ahrs_en 0 the hours alarm is disabled. 1 the hours alarm is enabled. 1 amin_en 0 the minutes alarm is disabled. 1 the minutes alarm is enabled. 0 asec_en 0 the seconds alarm is disabled. 1 the seconds alarm is enabled.
ps015309-1004 preliminary real-time clock ez80f92/ez80f93 product specification 103 the po wer -line frequenc y option is selected, the prescale v alue is set by freq_sel, and the 32 khz oscillator is disabled. see t able 53 . t able 53. real-t ime clock control registe r (r tc_ctrl = 00edh ) bit 7 6 5 4 3 2 1 0 reset x 0 x x x x 0/1 0 cpu access r r/w r/w r/w r/w r r r/w note: x = unchanged by reset; r = read only; r/w = read/write. bit position v alue description 7 alarm 0 alarm interrupt is inactive. 1 alarm interrupt is active. 6 int_en 0 interrupt on alarm condition is disabled. 1 interrupt on alarm condition is enabled. 5 bcd_en 0 rtc count and alarm value registers are binary. 1 rtc count and alarm value registers are binary-coded decimal ( bcd). 4 clk_sel 0 rtc clock source is crystal oscillator output (32768 hz). on-chip 32768hz oscillator is enabled. 1 rtc clock source is power-line frequency input. on-chip 32768 hz oscillator is disabled. 3 freq_sel 0 power-line frequency is 60 hz. 1 power-line frequency is 50 hz. 2 0 reserved. 1 slp_wake 0 rtc does not generate a sleep-mode recovery reset. 1 rtc alarm generates a sleep-mode recovery reset. 0 rtc_unlock 0 rtc count registers are locked to prevent write access. rtc counter is enabled. 1 rtc count registers are unlocked to allow write access. rtc counter is disabled.
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 104 universal asynchronous receiver/trans - mitter the u ar t module implements all of the logic required to support se v eral asynchronous communications protocols. the module also implements tw o separate 16-byte-deep fifos for both transmission and reception. a block diagram of the u ar t is illustrated in figure 24 . the u ar t module pro vides the follo wing asynchronous communication protocol-related features and functions: ? 5-, 6-, 7-, 8- or 9-bit data transmission ? ev en/odd, space/mark, or no parity bit generation and detection ? start and stop bit generation and detection ? supports up to tw o stop bits) ? line break detection and generation ? recei v er o v errun and framing errors detection ? logic and associated i/o to pro vide modem handshak e capability figure 24. uart block diagram system clock i/o address data receive buffer transmit buffer modem control logic interrupt signal to ez80 cpu uart control interface and baud rate generator rxd0/rxd1 txd0/txd1 cts0/cts1 rts0/rts1 dsr0/dsr1 dtr0/dtr1 dcd0/dcd1 ri0/ri1
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 105 uart functional description the u ar t function implements: ? the transmitter and associated control logic ? the recei v er and associated control logic ? the modem interf ace and associated logic uart functions the u ar t function implements: ? the transmitter and associated control logic ? the recei v er and associated control logic ? the modem interf ace and associated logic uart t ransmitter the transmitter block controls the data transmitted on the t x d output. it implements the fifo, accessed through the u ar tx_thr re gister , the transmit shift re gister , the parity generator , and control logic for the transmitter to control parameters for the asynchronous communication protocol. the u ar tx_thr is a write only re gister . the processor writes the data byte to be trans - mitted into this re gister . in the fifo mode, up to 16 data bytes can be written via the u ar tx_thr re gister . the data byte from the fifo is transferred to the transmit shift re g - ister at the appropriate time and transmitted out on t x d output. after sync_reset , the u ar tx_thr re gister is empty . therefore, the t ransmit holding re gister empty (thre) bit (bit 5 of the u ar tx_lsr re gister) is 1 and an interrupt is sent to the processor (if interrupts are enabled). the processor can reset this interrupt by loading data into the u ar tx_thr re gister , which clears the transmitter interrupt. the transmit shift re gister places the byte to be transmitted on the t x d signal serially . the least-signi? cant bit of the byte to be transmitted is shifted out ? rst and the most-signi? cant bit is shifted out last. the control logic within the block adds the asynchronous communi - cation protocol bits to the data byte being transmitted. the transmitter block obtains the parameters for the protocol from the bits programmed via the u ar tx_lctl re gister . when enabled, an interrupt is generated after the most recent protocol bit is transmitted, which the processor may reset by loading data into the u ar tx_thr re gister . the t x d output is set to 1 if the transmitter is idle (it does not contain an y data to be transmitted). the transmitter operates with the baud rate generator (brg) clock. the data bits are placed on the t x d output one time e v ery 16 brg clock c ycles. the transmitter block also implements a parity generator that attaches the parity bit to the byte, if programmed. f or
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 106 9-bit data, the host processor programs the parity bit generator so that it marks the byte as either address (mark parity) or data (space parity). uart receiver the recei v er block controls the data reception from the r x d signal. the recei v er block implements a recei v er shift re gister , recei v er line error condition monitoring logic and recei v er data ready logic. it also implements the parity check er . the u ar tx_rbr is a read only re gister of the module. the processor reads recei v ed data from this re gister . the condition of the u ar tx_rbr re gister is monitored by the dr bit (bit 0 of the u ar tx_lsr re gister). the dr bit is 1 when a data byte is recei v ed and transferred to the u ar tx_rbr re gister from the recei v er shift re gister . the dr bit is reset only when the processor reads all of the recei v ed data bytes. if the number of bits recei v ed is less than eight, the unused most-signi? cant bits of the data byte read are 0 f or 9-bit data, the recei v er checks incoming bytes for space parity . this check routine gen - erates a line status interrupt when an address byte is recei v ed, because address bytes con - tain mark parity bits. the processor clears the interrupt, determines if the address matches its o wn, then con? gures the recei v er to either accept the subsequent data bytes if the address matches, or ignore the data if it does not. the recei v er uses the clock from the brg for recei ving the data. this clock must be 16 times the appropriate baud rate. the recei v er synchronizes the shift clock on the f alling edge of the r x d input start bit. it then recei v es a complete byte according to the set parameters. the recei v er also implements logic to detect framing errors, parity errors, o v errun errors, and break signals. uart modem control the modem control logic pro vides tw o outputs and four inputs for handshaking with the modem. an y change in the modem status inputs, e xcept ri , is detected and an interrupt can be generated. f or ri , an interrupt is generated only when the trailing edge of the ri is detected. the module also pro vides loop mode for self-diagnostics. uart interrupts there are six dif ferent sources of interrupts from the u ar t . the six sources of interrupts are: ? t ransmitter (tw o dif ferent interrupts) ? recei v er (three dif ferent interrupts) ? modem status
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 107 uart t ransmitter interrupt the transmitter hold re gister empty interrupt is generated if there is no data a v ailable in the hold re gister . the transmission complete interrupt is generated after the data in the shift re gister is sent. both interrupts can be disabled using indi vidual interrupt enable bits or cleared by writing data into the u ar tx_thr re gister . uart receiver interrupts a recei v er interrupt can be generated by three possible sources. the ? rst source, a recei v er data ready , indicates that one or more data bytes are recei v ed and are ready to be read. this interrupt is generated if the number of bytes in the recei v er fifo is greater than or equal to the trigger le v el. if the fifo is not enabled, the interrupt is generated if the recei v e b uf fer contains a data byte. this interrupt is cleared by reading the u ar tx_rbr. the second interrupt source is the recei v er time-out. a recei v er time-out interrupt is gener - ated when there are fe wer data bytes in the recei v er fifo than the trigger le v el and there are no reads and writes to or from the recei v er fifo for four consecuti v e byte times. when the recei v er time-out interrupt is generated, it is cleared only after emptying the entire recei v e fifo. the ? rst tw o interrupt sources from the recei v er (data ready and time-out) share an inter - rupt enable bit. the third source of a recei v er interrupt is a line status error , indicating an error in byte reception. this error may result from: ? incorrect recei v ed parity . f or 9-bit data, incorr ect parity indicates detection of an address byte ? incorrect framing; that is, the stop bit is not detected by recei v er at the end of the byte ? recei v er o v er run condition ? a break condition being detected on the recei v e data input an interrupt due to one of the abo v e conditions is cleared when the u ar tx_lsr re gister is read. in fifo mode, a line status interrupt is generated only after the recei v ed byte with an error reaches the top of the fifo and is ready to be read. a line status interrupt is acti v ated (pro vided this interrupt is enabled) as long as the read pointer of the recei v er fifo points to the location of the fifo that contains a byte with the error . the interrupt is immediately cleared when the u ar tx_lsr re gister is read. the err bit of the u ar tx_lsr re gister is acti v e as long as an erroneous byte is present in the recei v er fifo. uart modem status interrupt the modem status interrupt is generated if there is an y change in state of the modem status inputs to the u ar t . this interrupt is cleared when the processor reads the u ar tx_msr re gister .
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 108 uart recommended usage the follo wing is the standard sequence of e v ents that occur in the ez80f92 de vice using the u ar t . a description of each follo ws. ? module reset ? control transfers to con? gure u ar t operation ? data transfers module reset upon reset, all internal re gisters are set to their def ault v alues. all command status re gis - ters are programmed with their def ault v alues, and the fifos are ? ushed. control t ransfers based on the requirements of the application, the data transfer baud rate is determined and the brg is con? gured to generate a 16x clock frequenc y . interrupts are disabled and the communication control parameters are programmed in the u ar tx_lctl re gister . the fifo con? guration is determined and the recei v e trigger le v els are set in the u ar tx_fctl re gister . the status re gisters, u ar tx_lsr and u ar tx_msr, are read, and ensure that none of the interrupt sources are acti v e. the interrupts are enabled (e xcept for the transmit interrupt) and the application is ready to use the module for transmission/ reception. data t ransfers t ransmit . t o transmit data, the application enables the transmit interrupt. an interrupt is immediately e xpected in response. the application reads the u ar tx_iir re gister and determines whether the interrupt occurs due to an empty u ar tx_thr re gister or due to a completed transmission. upon this determination, the application writes the pertinent transmit data bytes to the u ar tx_thr re gister . the number of bytes that the application writes depends on whether or not the fifo is enabled. if the fifo is enabled, the applica - tion can write 16 bytes at a time. if not, the application can write one byte at a time. as a result of the ? rst write, the interrupt is deacti v ated. the processor then w aits for the ne xt interrupt. when the interrupt is raised by the u ar t module, the processor repeats the same process until it e xhausts all of the data for transmission. t o control and check the modem status, the application sets up the modem by writing to the u ar tx_mctl re gister and reading the u ar tx_mctl re gister before starting the process mentioned abo v e. receive . the recei v er is al w ays enabled, and it continually checks for the start bit on the r x d input signal. when an interrupt is raised by the u ar t module, the application reads the u ar tx_iir re gister and determines the cause for the interrupt. if the cause is a line status interrupt, the application reads the u ar tx_lsr re gister , reads the data byte and
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 109 then can discard the byte or tak e other appropriate action. if the interrupt is caused by a recei v e-data-ready condition, the application alternately reads the u ar tx_lsr and u ar tx_rbr re gisters and remo v es all of the recei v ed data bytes. it reads the u ar tx_lsr re gister before reading the u ar tx_rbr re gister to determine that there is no error in the recei v ed data. t o control and check modem status, the application sets up the modem by writing to the u ar tx_mctl re gister and reading the u ar tx_msr re gister before starting the process mentioned abo v e. poll mode t ransfers . when interrupts are disabled, all data transfers are referred to as poll mode transfers. in poll mode transfers, the application must continually poll the u ar tx_lsr re gister to transmit or recei v e data without enabling the interrupts. the same is true for the u ar tx_msr re gister . if the interrupts are not enabled, the data in the u ar tx_iir re gister cannot be used to determine the cause of an interrupt. baud rate generator the baud rate generator consists of a 16-bit do wncounter , tw o re gisters, and associated decoding logic. the initial v alue of the baud rate generator is de? ned by the tw o brg di visor latch re gisters, {u ar tx_brg_h, u ar tx_brg_l}. at the rising edge of each system clock, the brg decrements until it reaches the v alue 0001h . on the ne xt system clock rising edge, the brg reloads the initial v alue from {u ar tx_brg_h, u ar tx_brg_l) and outputs a pulse to indicate the end-of-count. calculate the u ar t data rate with the follo wing equation: upon reset , the 16-bit brg di visor v alue resets to 0002h . a minimum brg di visor v alue of 0001h is also v alid, and ef fecti v ely bypasses the brg. a softw are write to either the lo w- or high-byte re gisters for the brg di visor latch causes both the lo w and high bytes to load into the brg counter , and causes the count to restart. the di visor re gisters can only be accessed if bit 7 of the u ar t line control re gister ( uart x _lctl ) is set to 1. after reset, this bit is reset to 0. recommended usage of the baud rate generator the follo wing is the normal sequence of operations that should occur after the ez80f92 de vice is po wered on to con? gure the baud rate generator: ? assert and deassert reset ? set u ar tx_lctl[7] to 1 to enable access of the brg di visor re gisters uart data rate (bits/s) = system clock frequency 16 x (uar t baud rate generator divisor)
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 110 ? program the u ar tx_brg_l and u ar tx_brg_h re gisters ? clear u ar tx_lctl[7] to 0 to disable access of the brg di visor re gisters brg control registers uart baud rate generator registerlow and high bytes the re gisters hold the lo w and high bytes of the 16-bit di visor count loaded by the pro - cessor for u ar t baud rate generation. the 16-bit clock di visor v alue is returned by {u ar t x _brg_h, u ar t x _brg_l}, where x is either 0 or 1 to identify the tw o a v ailable u ar t de vices. upon reset , the 16-bit brg di visor v alue resets to 0002h . the initial 16-bit di visor v alue must be between 0002h and ffffh as the v alues 0000h and 0001h are in v alid, and proper operation is not guaranteed. as a result, the minimum brg clock di visor ratio is 2. a write to either the lo w- or high-byte re gisters for the brg di visor latch causes both bytes to be loaded into the brg counter . the count is then restarted. bit 7 of the associated u ar t line control re gister (u ar t x _lctl) must be set to 1 to access this re gister . see t ables 54 and 55 . refer to the u ar t line control re gister (u ar tx_lctl) on page 116 for more information. the u ar tx_brg_l re gisters share the same address space with the u ar tx_rbr and u ar tx_thr re gisters. the u ar tx_brg_h re gisters share the same address space with the u ar tx_ier re gisters. bit 7 of the associated u ar t line control re gister (u ar tx_lctl) must be set to 1 to enable access to the brg re gisters. t able 54. uart baud rate generator registerlow byte s (u art0_brg_l = 00c0h, uart1_brg_l = 00d0h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 1 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r = read only; r/w = read/write. bit position v alue description [7:0] uar t_brg_l 00hC ffh these bits represent the low byte of the 16-bit baud rate generator divider value. the complete brg divisor value is returned by {uart_brg_h, uart_brg_l}. note:
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 111 uart registers after a reset , all u ar t re gisters are set to their def ault v alues. an y writes to unused re gisters or re gister bits are ignored and reads return a v alue of 0. f or compatibility with future re visions, unused bits within a re gister should al w ays be written with a v alue of 0. read/write attrib utes, reset conditions, and bit descriptions of all of the u ar t re gisters are pro vided in this section. uart t ransmit holding register if less than eight bits are programmed for transmission, the lo wer bits of the byte written to this re gister are selected for transmission. the transmit fifo is mapped at this address. the user can write up to 16 bytes for transmission at one time to this address if the fifo is enabled by the application. if the fifo is disabled, this b uf fer is only one byte deep. these re gisters share the same address space as the u ar tx_rbr and u ar tx_brg_l re gisters. see t able 56 . t able 55. uart baud rate generator registerhigh byte s (u art0_brg_h = 00c1h, uart1_brg_h = 00d1h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r = read only; r/w = read/write. bit position v alue description [7:0] uar t_brg_h 00hC ffh these bits represent the high byte of the 16-bit baud rate generator divider value. the complete brg divisor value is returned by {uart_brg_h, uart_brg_l}.
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 112 uart receive buffer register the bits in this re gister re? ect the data recei v ed. if less than eight bits are programmed for recei v e, the lo wer bits of the byte re? ect the bits recei v ed whereas upper unused bits are 0. the recei v e fifo is mapped at this address. if the fifo is disabled, this b uf fer is only one byte deep. these re gisters share the same address space as the u ar tx_thr and u ar tx_brg_l re gisters. see t able 57 . t able 56. uart t ransmit holding register s (u art0_thr = 00c0h, uart1_thr = 00d0h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: w = write only. bit position v alue description [7:0] t x d 00hC ffh transmit data byte. t able 57. uart receive buffer register s (u art0_rbr = 00c0h, uart1_rbr = 00 d0h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] r x d 00hC ffh receive data byte.
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 113 uart interrupt enable register the u ar tx_ier re gister is used to enable and disable the u ar t interrupts. the u ar tx_ier re gisters share the same i/o addresses as the u ar tx_brg_h re gisters. see t able 58 . t able 58. uart interrupt enable register s (u art0_ier = 00c1h, uart1_ier = 00d1h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r/w r/w r/w r/w r/w note: r = read only; r/w = read/write. bit position v alue description [7:5] 000 reserved. 4 tcie 0 transmission complete interrupt is disabled. 1 transmission complete interrupt is generated when both the transmit hold register and the transmit shift register are empty. 3 miie 0 modem interrupt on edge detect of status inputs is disabled. 1 modem interrupt on edge detect of status inputs is enabled. 2 lsie 0 line status interrupt is disabled. 1 line status interrupt is enabled for receive data errors: incorrect parity bit received, framing error, overrun error, or break detection. 1 tie 0 transmit interrupt is disabled. 1 transmit interrupt is enabled. interrupt is generated when the transmit fifo/buffer is empty indicating no more bytes available for transmission. 0 rie 0 receive interrupt is disabled. 1 receive interrupt and receiver time-out interrupt are enabled. interrupt is generated if the fifo/buffer contains data ready to be read or if the receiver times out.
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 114 uart interrupt identification register the read only u ar tx_iir re gister allo ws the user to check whether the fifo is enabled and the status of interrupts. these re gisters share the same i/o addresses as the u ar tx_fctl re gisters. see t ables 59 and 60 . t able 59. uart interrupt identification register s (u art0_iir = 00c2h, uart1_iir = 00d2h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 1 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:6] fsts 00 fifo is disabled. 10 receive fifo is disabled ( multidrop mode). 11 fifo is enabled. [5:4] 00 reserved. [3:1] insts 000C 110 interrupt status code the code indicated in these three bits is valid only if intbit is 1. if two internal interrupt sources are active and their respective enable bits are high, only the higher priority interrupt is seen by the application. the lower-priority interrupt code is indicated only after the higher-priority interrupt is serviced. t able 60 lists the interrupt status codes. 0 intbit 0 there is an active interrupt source within the uart. 1 there is not an active interrupt source within the uart. t able 60. uart interrupt status codes insts v alue priority interrupt t ype 011 highest receiver line status 010 second receiver data ready or trigger level 110 third character time-out 101 fourth transmission complete
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 115 uart fifo control register this re gister is used to monitor trigger le v els, clear fifo pointers, and enable or disable the fifo. the u ar tx_fctl re gisters share the same i/o addresses as the u ar tx_iir re gisters. see t able 61 . 001 fifth transmit buffer empty 000 lowest modem status t able 61. uart fifo control register s (u art0_fctl = 00c2h, uart1_fctl = 00d2h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write only. bit position v alue description [7:6] trig 00 receive fifo trigger level set to 1. receive data interrupt is generated when there is 1 byte in the fifo. valid only if fifo is enabled. 01 receive fifo trigger level set to 4. receive data interrupt is generated when there are 4 bytes in the fifo. valid only if fifo is enabled. 10 receive fifo trigger level set to 8. receive data interrupt is generated when there are 8 bytes in the fifo. valid only if fifo is enabled. 11 receive fifo trigger level set to 14. receive data interrupt is generated when there are 14 bytes in the fifo. valid only if fifo is enabled. [5:3] 000 reserved. 2 clrtxf 0 no effect. 1 clear the transmit fifo and reset the transmit fifo pointer. valid only if the fifo is enabled. note: *receive fifo is not enabled during multidrop mode. t able 60. uart interrupt status codes (continued) insts v alue priority interrupt t ype
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 116 uart line control register this re gister is used to control the communication control parameters. see t ables 62 and 63 . 1 clrrxf 0 no effect. 1 clear the receive fifo, clear the receive error fifo, and reset the receive fifo pointer. valid only if the fifo is enabled. 0 fifoen 0 transmit and receive fifos are disabled. transmit and receive buffers are only 1 byte deep. 1 transmit and receive fifos are enabled*. t able 62. uart line control register s (u art0_lctl = 00c3h, uart1_lctl = 00d3h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description 7 dlab 0 access to the uart registers at i/o addresses uartx_rbr, uartx_thr, and uartx_ier is enabled. 1 access to the baud rate generator registers at i/o addresses uartx_brg_l and uartx_brg_h is enabled. note: *receive parity is set to space in multidrop mode. bit position v alue description note: *receive fifo is not enabled during multidrop mode.
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 117 6 sb 0 do not send a break signal. 1 send break uart sends continuous zeroes on the transmit output from the next bit boundary. the transmit data in the transmit shift register is ignored. after forcing this bit high, the t x d output is 0 only after the bit boundary is reached. just before forcing t x d to 0, the transmit fifo is cleared. any new data written to the transmit fifo during a break should be written only after the thre bit of uartx_lsr register goes high. this new data is transmitted after the uart recovers from the break. after the break is removed, the uart recovers from the break for the next brg edge. 5 fpe 0 do not force a parity error. 1 force a parity error. when this bit and the party enable bit ( pen ) are both 1, an incorrect parity bit is transmitted with the data byte. 4 eps 0 use odd parity for transmit and receive. the total number of 1 bits in the transmit data plus parity bit is odd. use as a space bit in multidrop mode. see table 64 for parity select definitions.* 1 use even parity for transmit and receive. the total number of 1 bits in the transmit data plus parity bit is even. use as a mark bit in multidrop mode. see table 64 for parity select definitions. 3 pen 0 parity bit transmit and receive is disabled. 1 parity bit transmit and receive is enabled. for transmit, a parity bit is generated and transmitted with every data character. for receive, the parity is checked for every incoming data character. in multidrop mode, receive parity is checked for space parity. [2:0] char 000C 111 uart character parameter selections ee table 63 for a description of the values. bit position v alue description note: *receive parity is set to space in multidrop mode.
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 118 t able 63. uart character parameter definition char[2:0] character length (tx/rx data bits) stop bits (tx stop bits) 000 5 1 001 6 1 010 7 1 011 8 1 100 5 2 101 6 2 110 7 2 111 8 2 t able 64. parity select definition for multidrop communications mdm uartx_mgtl[5] eps uartx_lctl940 parity t ype 0 0 odd 0 1 even 1 0 space 1 1* mark note: *in multidrop mode, eps resets to 0 after the first character is sent.
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 119 uart modem control register this re gister is used to control and check the modem status, as detailed in t able 65 . t able 65. uart modem control register s (u art0_mctl = 00c4h, uart1_mctl = 00d4h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r/w r/w r/w r/w r/w r/w note: r = read only; r/w = read/write. bit position v alue description [7:6] 00b reservedmust be 00b. 5 mdm 0 multidrop mode disabled. 1 multidrop mode enabled. see table 64 for parity select definitions. 4 loop 0 loop back mode is not enabled. 1 loop back mode is enabled. the uart operates in internal loop back mode. the transmit data output port is disconnected from the internal transmit data output and set to 1. the receive data input port is disconnected and internal receive data is connected to internal transmit data. the modem status input ports are disconnected and the four bits of the modem control register are connected as modem status inputs. the two modem control output ports (out1&2) are set to their inactive state 3 out2 0C1 no function in normal operation. in loop back mode, this bit is connected to the dcd bit in the uart status register. 2 out1 0C1 no function in normal operation. in loop back mode, this bit is connected to the ri bit in the uart status register. 1 rts 0C1 request to send in normal operation, the rts output port is the inverse of this bit. in loop back mode, this bit is connected to the cts bit in the uart status register. 0 dtr 0C1 data terminal ready in normal operation, the dtr output port is the inverse of this bit. in loop back mode, this bit is connected to the dsr bit in the uart status register.
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 120 uart line status register this re gister is used to sho w the status of u ar t interrupts and re gisters. see t able 66 . t able 66. uart line status register s (u art0_lsr = 00c5h, uart1_lsr = 00 d5h ) bit 7 6 5 4 3 2 1 0 reset 0 1 1 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description 7 err 0 always 0 when operating in with the fifo disabled. with the fifo enabled, this bit is reset when the uartx_lsr register is read and there are no more bytes with error status in the fifo. 1 error detected in the fifo. there is at least 1 parity, framing or break indication error in the fifo. 6 temt 0 transmit holding register/fifo is not empty or transmit shift register is not empty or transmitter is not idle. 1 transmit holding register/fifo and transmit shift register are empty; and the transmitter is idle. this bit cannot be set to 1 during the break condition. this bit only becomes 1 after the break command is removed. 5 thre 0 transmit holding register/fifo is not empty. 1 transmit holding register/fifo is empty. this bit cannot be set to 1 during the break condition. this bit only becomes 1 after the break command is removed. 4 bi 0 receiver does not detect a break condition. this bit is reset to 0 when the uartx_lsr register is read. 1 receiver detects a break condition on the receive input line. this bit is 1 if the duration of break condition on the receive data is longer than one character transmission time, the time depends on the programming of the uartx_lsr register. in case of fifo only one null character is loaded into the receiver fifo with the framing error. the framing error is revealed to the cpu whenever that particular data is read from the receiver fifo.
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 121 uart modem status register this re gister is used to sho w the status of the u ar t signals. see t able 67 . 3 fe 0 no framing error detected for character at the top of the fifo. this bit is reset to 0 when the uartx_lsr register is read. 1 framing error detected for the character at the top of the fifo. this bit is set to 1 when the stop bit following the data/ parity bit is logic 0. 2 pe 0 the received character at the top of the fifo does not contain a parity error. in multidrop mode, this indicates that the received character is a data byte. this bit is reset to 0 when the uartx_lsr register is read. 1 the received character at the top of the fifo contains a parity error. in multidrop mode, this indicates that the received character is an address byte. 1 oe 0 the received character at the top of the fifo does not contain an overrun error. this bit is reset to 0 when the uartx_lsr register is read. 1 overrun error is detected. if the fifo is not enabled, this indicates that the data in the receive buffer register was not read before the next character was transferred into the receiver buffer register. if the fifo is enabled, this indicates the fifo was already full when an additional character was received by the receiver shift register. the character in the receiver shift register is not put into the receiver fifo. 0 dr 0 this bit is reset to 0 when the uartx_rbr register is read or all bytes are read from the receiver fifo. 1 data ready if the fifo is not enabled, this bit is set to 1 when a complete incoming character is transferred into the receiver buffer register from the receiver shift register. if the fifo is enabled, this bit is set to 1 when a character is received and transferred to the receiver fifo. bit position v alue description
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 122 t able 67. uart modem status register s (u art0_msr = 00c6h, uart1_msr = 00 d6h ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r r r r r r r r note: r = read only. bit position v alue description 7 dcd 0C1 data carrier detect in normal mode, this bit reflects the inverted state of the dcdx input pin. in loop back mode, this bit reflects the value of the uartx_mctl[3] = out2. 6 ri 0C1 ring indicator in normal mode, this bit reflects the inverted state of the rix input pin. in loop back mode, this bit reflects the value of the uartx_mctl[2] = out1. 5 dsr 0C1 data set ready in normal mode, this bit reflects the inverted state of the dsrx input pin. in loop back mode, this bit reflects the value of the uartx_mctl[0] = dtr. 4 cts 0C1 clear to send in normal mode, this bit reflects the inverted state of the ctsx input pin. in loop back mode, this bit reflects the value of the uartx_mctl[1] = rts. 3 ddcd 0C1 delta status change of dcd this bit is set to 1 whenever the dcdx pin changes state. this bit is reset to 0 when the uartx_msr register is read. 2 teri 0C1 trailing edge change on ri this bit is set to 1 whenever a falling edge is detected on the rix pin. this bit is reset to 0 when the uartx_msr register is read. 1 ddsr 0C1 delta status change of dsr this bit is set to 1 whenever the dsrx pin changes state. this bit is reset to 0 when the uartx_msr register is read. 0 dcts 0C1 delta status change of cts this bit is set to 1 whenever the ctsx pin changes state. this bit is reset to 0 when the uartx_msr register is read.
ps015309-1004 preliminary universal asynchronous receiver/transmitter ez80f92/ez80f93 product specification 123 uart scratch pad register the u ar tx_spr re gister can be used by the system as a general-purpose read/write re g - ister . see t able 68 . t able 68. uart scratch pad register s (u art0_spr = 00c7h, uart1_spr = 00d7h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] spr 00hC ffh the uart scratch pad register is available for use as a general-purpose read/write register.
ps015309-1004 preliminary infrared encoder/decoder ez80f92/ez80f93 product specification 124 infrared encoder/decoder the ez80f92 de vice contains a u ar t to infrared encoder/decoder ( endec). the ird a endec is inte grated with the on-chip u ar t0 to allo w easy communication between the cpu and ird a ph ysical layer speci? cation v ersion 1.4-compatible infrared transcei v ers, as illustrated in figure 25 . infrared communication pro vides secure, reliable, high-speed, lo w-cost, point-to-point communication between pcs, pd as, mobile telephones, printers, and other infrared-enabled de vices. functional description when the ird a endec is enabled, the transmit data from the on-chip u ar t is encoded as digital signals in accordance with the ird a standard and output to the infrared transcei v er . lik e wise, data recei v ed from the infrared transcei v er is decoded by the endec and passed to the u ar t . communication is half-duple x, meaning that simultaneous data transmission and reception is not allo wed. the baud rate is set by the u ar t baud rate generator , and supports ird a standard baud rates from 9600 bps to 115.2 kbps. higher baud rates than 115.2 kbps are possible, b ut do not meet ird a speci? cations for these data rates. the u ar t must be enabled to use the figure 25. infrared system block diagram ez80f92 to ez80 cpu system clock uart0 rxd txd rxd txd ir_rxd ir_txd baud rate clock infrared encoder/decoder interrupt signal i/o address data i/o address data infrared transceiver
ps015309-1004 preliminary infrared encoder/decoder ez80f92/ez80f93 product specification 125 endec. refer to the uni v ersal asynchronous recei v er/t ransmitter section on page 104 for more information about t he u ar t and its baud rate generator . transmit the data to be transmitted via the ir transcei v er is ? rst sent to u ar t0. the u ar t trans - mit signal ( t x d ) and baud rate clock are used by the ird a endec to generate the modu - lation signal ( ir_txd) that dri v es the infrared transcei v er . t o enable transmit encoding, the ir_rxen bit in the ir_ctl re gister must be set to 0. each u ar t bit is 16-clocks wide. if the data to be transmitted is a logical 1 (high), the ir_txd signal remains lo w (0) for the full 16-clock period. if the data to be transmitted is a logical 0, a 3-clock high (1) pulse is output follo wing a 7-clock lo w (0) period. f ollo w - ing the 3-clock high pulse, a 6-clock lo w pulse completes the full 16-clock data period. data transmission is illustrated in figure 26 . during data transmission, the ir recei v e function should be disabled by clearing the ir_rxen bit in the ir_ctl re g to 0. the sir data format uses half-duple x communication; the u ar t does not transmit data while the recei v er decoder is enabled. receive data is recei v ed from the ir transcei v er via the ir_rxd signal and decoded by the ird a endec. this decoded data is passed from the endec to u ar t0. t o enable recei v er decode, the ir_rxen bit in the ir_ctl re gister must be set to 1. the sir data format uses half- duple x communication; therefore, the u ar t should not transmit data during normal oper - ation while the recei v er decoder is enabled. figure 26. infrared data t ransmission 16-clock period 3-clock pulse 7-clock delay baud rate clock uart_txd start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 ir_txd
ps015309-1004 preliminary infrared encoder/decoder ez80f92/ez80f93 product specification 126 the u ar t baud rate clock is used by the ird a endec to generate the demodulated signal (rxd) that dri v es the u ar t . each u ar t bit period is sixteen baud-clocks wide. each ir_rxd bit is encoded during a bit period such that a 0 is represented by a pulse and a 1 is represented by no pulse. the ird a ph ysical layer speci? cation describes a nominal pulse as being 3 / 16 of a bit period wide. in this case, if the data to be recei v ed is a logical 0 (lo w), a 3-clock-wide lo w (0) pulse is recei v ed follo wing a 7-clock high (1) period. f ol - lo wing the 3-clock lo w pulse is a 6-clock high pulse to complete the full 16-clock data period. if the data to be recei v ed is a logical 1 (high), the ir_rxd signal is held high (1) for the full 16-clock period. data reception is illustrated in figure 27 . the ird a ph ysical layer speci? cation allo ws for a minimum signal width as well as the nominal signal width described abo v e. by de? nition, the recei v ed pulse duration can be as small as 1.41 seconds for all baud rates up to 115.2 kbps. t able 69 outlines the minimum and maximum pulse durations for all baud rates supported by the ez80 ? cpu. a recei v er frequenc y di vider based upon the system clock frequenc y measures this time limit and allo ws le g al signals to pass to u ar t0. figure 27. infrared data reception t able 69. irda physical layer 1.4 pulse durations specifications baud rate minimum pulse w idth maximum pulse w idth 9600 1.41 s 22.13 s 19200 1.41 s 1 1.07 s 38400 1.41 s 5.96 s 16-clock period 16-clock period 16-clock period 16-clock period 1.4 s min. pulse 8-clock delay baud rate clock rxd start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 rxd 16-clock period ir uart
ps015309-1004 preliminary infrared encoder/decoder ez80f92/ez80f93 product specification 127 receiver frequency divider the ird a recei v er uses a 6-bit frequenc y di vider . the v alue is deri v ed from the system clock to measure ir_rxd pulses. the ird a endec detects pulses that are within the ird a ph ysical layer speci? ed minimum and maximum ranges, with system clock frequencies from 5 mhz up to 50 mhz. the upper four bits of the frequenc y di vider f actor are set via the freq_div bit in the ir_ctl re gister , based on the follo wing equation: the remaining lo wer tw o bits of the di vider are set to 03h . the tar get frequenc y corre - sponds to a period of 1.2 seconds. the freq_div v alue must be rounded to the nearest inte ger and the resulting period of the 6-bit frequenc y di vider must not be lar ger than 1.4 seconds, which is the ird a de? ned minimum pulse width. if the period is greater than 1.4 seconds, freq_div should be rounded to the ne xt lo wer inte ger . the recei v er frequenc y di vider v alue v ersus the system clock frequenc y is sho wn in t able 2, belo w . 57600 1.41 s 4.34 s 1 15200 1.41 s 2.23 s frequency divider factor = system clock frequency (mhz) target frequency of 3.33 mhz t able 70. frequency divider v alues system clock freq_div < 5.0 mhz 00h* 5.0C7.8 mhz 01h 7.8C10.8 mhz 02h 10.8C13.6 mhz 03h 13.6C25 mhz floor[4-bit frequency divider factor] 25C50 mhz round[4-bit frequency divider factor] note: *the frequency divider is disabled when set to 00h. t able 69. irda physical layer 1.4 pulse durations specifications baud rate minimum pulse w idth maximum pulse w idth
ps015309-1004 preliminary infrared encoder/decoder ez80f92/ez80f93 product specification 128 setting the upper 4 bits of ir_ctl to 00h disables the frequenc y di vider b ut not the ird a recei v er . in this mode, the ird a recei v er uses edge detection on the ir_rxd bit stream. jitter due to the inherent sampling of the recei v ed ir_rxd signal by the bit rate clock, some jitter can be e xpected on the ? rst bit in an y sequence of data. ho we v er , all subsequent bits in the recei v ed data stream are a ? x ed 16 clock periods wide. infrared encoder/decoder signal pins the ird a endec signal pins ( ir_txd and ir_rxd) are multiple x ed with general-purpose i/o (gpio) pins. these gpio pins must be con? gured for alternate function operation for the endec to operate. the remaining six u ar t0 pins ( cts0 , dcd0 , dsr0 , dtr0 , r ts and ri0 ) are not required for use with the endec. the u ar t0 modem status interrupt should be disabled to pre v ent unw anted interrupts from these pins. the gpio pins corresponding to these six unused u ar t0 pins can be used for inputs, outputs, or interrupt sources. recommended gpio port d control re gister settings are pro vided in t able 71 . refer to the general-pur - pose input/output section on page 40 for additional information about s etting the gpio port modes. loopback testing both internal and e xternal loopback testing can be accomplished with the ird a endec on the ez80f92 de vice. setting the loop_b a ck bit to 1 enables internal loopback testing. during internal loopback, the ir_txd output signal is inverted and connected on-chip to the ir_rxd input. external loopback testing of the of f-chip ird a transcei v er can be accomplished by transmitting data from the u ar t while the recei v er is enabled (ir_rxen set to 1). t able 71. gpio mode selection when using the irda encoder/decoder gpio port d bits allowable gpio port mode allowable port mode functions pd0 7 alternate function. pd1 7 alternate function. pd2Cpd7 any other than gpio mode 7 (1, 2, 3, 4, 5, 6, 8, or 9) output, input, open-drain, open-source, level- sensitive interrupt input, or edge-triggered interrupt input.
ps015309-1004 preliminary infrared encoder/decoder ez80f92/ez80f93 product specification 129 infrared encoder/decoder register after a reset , the infrared encoder/decoder re gister is set to its def ault v alue. an y writes to unused re gister bits are ignored and reads return a v alue of 0. the ir_ctl re gis - ter is described in t able 72 . t able 72. infrared encoder/decoder control register s (i r_ctl = 00bfh ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r = read only; r/w = read/write. bit position v alue description [7:3] 000000 reserved. 2 loop_back 0 internal loop back mode is disabled. 1 internal loop back mode is enabled. ir_txd output is inverted and connected to ir_rxd input for internal loop back testing. 1 ir_rxen 0 ir_rxd data is ignored. 1 ir_rxd data is passed to uart0 r x d . 0 ir_en 0 irda endec is disabled. 1 irda endec is enabled.
ps015309-1004 preliminary serial peripheral interface ez80f92/ez80f93 product specification 130 serial peripheral interface the serial peripheral interf ace ( spi) is a synchronous interf ace allo wing se v eral spi-type de vices to be interconnected. the spi is a full-duple x, synchronous, character -oriented communication channel that emplo ys a four -wire interf ace. the spi block consists of a transmitter , recei v er , baud rate generator , and control unit. during an spi transfer , data is sent and recei v ed simultaneously by both the master and the sla v e spi de vices. in a serial peripheral interf ace, separate signals are required for data and clock. the spi may be con? gured as either a master or a sla v e. the connection of tw o spi de vices (one master and one sla v e) and the direction of data transfer is demonstrated in figures 28 and 29 . figure 28. spi master device figure 29. spi slave device master miso dataout clkout ss bit 0 8-bit shift register baud rate generator bit 7 sck datain slave mosi miso sck dataout ss bit 0 8-bit shift register bit 7 datain enable clkin
ps015309-1004 preliminary serial peripheral interface ez80f92/ez80f93 product specification 131 spi signals the four basic spi signals are: ? miso (master in, sla v e out) ? mosi (master out, sla v e in) ? sck (spi serial clock) ? ss (sla v e select) these spi signals are discussed in the follo wing paragraphs. each signal is described in both master and sla ve modes. master in, slave out the master in, sla v e out (miso) pin is con? gured as an input in a master de vice and as an output in a sla v e de vice. it is one of the tw o lines that transfer serial data, with the most- signi? cant bit sent ? rst. the miso pin of a sla v e de vice is placed in a high-impedance state if the sla v e is not selected. when the spi is not enabled, this signal is in a high- impedance state. master out, slave in the master out, sla v e in (mosi) pin is con? gured as an output in a master de vice and as an input in a sla v e de vice. it is one of the tw o lines that transfer serial data, with the most- signi? cant bit sent ? rst. when the spi is not enabled, this signal is in a high-impedance state. slave select the acti v e lo w sla v e select ( ss ) input signal is used to select the spi as a sla v e de vice. it must be lo w prior to all data communication and must stay lo w for the duration of the data transfer . the ss input signal must be high for the spi to operate as a master de vice. if the ss signal goes lo w , a mode f ault error ? ag ( modf) is set in the spi_sr re gister . see the spi sta - tus re gister (spi_sr) on page 138 for more information. when the clock phase bit ( cpha) is set to 0, the shift clock is the logical or of ss with sck. in this clock phase mode, ss must go high between successi v e characters in an spi message. when cpha is set to 1, ss can remain lo w for se v eral spi characters. in cases where there is only one spi sla v e, its ss line could be tied lo w as long as cpha is set to 1. see the spi control re gister (spi_ctl) on page 137 for more information about c pha. serial clock the serial clock (sck) is used to synchronize data mo v ement both in and out of the de vice through its mosi and miso pins. the master and sla v e are each capable of
ps015309-1004 preliminary serial peripheral interface ez80f92/ez80f93 product specification 132 e xchanging a byte of data during a sequence of eight clock c ycles. because sck is gener - ated by the master , the sck pin becomes an input on a sla v e de vice. the spi contains an internal di vide-by-tw o clock di vider . in master mode, the spi serial clock is one-half the frequenc y of the clock signal created by the spi s baud rate generator . as demonstrated in figure 30 and t able 73 , four possible timing relations may be chosen by using control bits cpol and cpha in the spi control re gister . see the spi control re gister (spi_ctl) on page 137 . both the master and sla v e must operate with the identi - cal timing, clock polarity (cpol), and clock phase (cpha). the master de vice al w ays places data on the mosi line a half-c ycle before the clock edge (sck signal) so that the sla v e de vice latches the data. figure 30. spi t iming t able 73. spi clock phase and clock polarity operation cpha cpol sck t ransmit edge sck receive edge sck idle state ss high between characters? 0 0 falling rising low y es 0 1 rising falling high y es 1 0 rising falling low no 1 1 falling rising high no sck (cpol bit = 0) sck (cpol bit = 1) sample input (cpha bit = 0) data out sample input (cpha bit = 1) data out enable (to slave) number of cycles on the sck signal 1234 5678 msb 6 5 4 3 2 1 lsb msb 6 5 4 3 2 1 lsb
ps015309-1004 preliminary serial peripheral interface ez80f92/ez80f93 product specification 133 spi functional description when a master transmits to a sla v e de vice via the mosi signal, the sla v e de vice responds by sending data to the master via the master's miso signal. the resulting implication is a full-duple x transmission, with both data out and data in synchronized with the same clock signal. thus the byte transmitted is replaced by the byte recei v ed and eliminates the requirement for separate transmit-empty and recei v e-full status bits. a single status bit, spif , is used to signify that the i/o operation is completed, see the spi status re gister (spi_sr) on page 138 . the spi is double-b uf fered on read, b ut not on write. if a write is performed during data transfer , the transfer occurs uninterrupted, and the write is unsuccessful. this condition causes the write collision ( wcol) status bit in the spi_sr re gister to be set. after a data byte is shifted, the spif ? ag of the spi_sr re gister is set. in spi master mode, the sck pin functions as an output. it idles high or lo w , depend - ing on the cpol bit in the spi_ctl re gister , until data is written to the shift re gister . data transfer is initiated by writing to the transmit shift re gister , spi_tsr. eight clocks are then generated to shift the eight bits of transmit data out the mosi pin while shifting in eight bits of data on the miso pin. after transfer , the sck signal idles. in spi sla ve mode, the start logic recei v es a logic lo w from the ss pin and a clock input at the sck pin, and the sla v e is synchronized to the master . data from the master is recei v ed serially from the sla v e mosi signal and loads the 8-bit shift re gister . after the 8- bit shift re gister is loaded, its data is parallel transferred to the read b uf fer . during a write c ycle data is written into the shift re gister , then the sla v e w aits for the spi master to initiate a data transfer , supply a clock signal, and shift the data out on the sla v e's miso signal. if the cpha bit in the spi_ctl re gister is 0, a transfer be gins when ss pin signal goes lo w and the transfer ends when ss goes high after eight clock c ycles on sck. when the cpha bit is set to 1, a transfer be gins the ? rst time sck becomes acti v e while ss is lo w and the transfer ends when the spif ? ag gets set. spi flags mode fault the mode f ault ? ag ( modf ) indicates that there may be a multimaster con? ict for sys - tem control. the modf bit is normally cleared to 0 and is only set to 1 when the master de vice s ss pin is pulled lo w . when a mode f ault is detected, the follo wing occurs: 1. the modf ? ag (spi_sr[4]) is set to 1. 2. the spi de vice is disabled by clearing the spi_en bit (spi_ctl[5]) to 0. 3. the master_en bit (spi_ctl[4]) is cleared to 0, forcing the de vice into slave mode.
ps015309-1004 preliminary serial peripheral interface ez80f92/ez80f93 product specification 134 4. if the spi interrupt is enabled by setting irq_en (spi_ctl[7]) high, an spi interrupt is generated. clearing the mode f ault ? ag is performed by reading the spi status re gister . the other spi control bits ( spi_en and master_en ) must be restored to their original states by user softw are after the mode f ault ? ag is cleared. w rite collision the write collision ? ag, wcol (spi_sr[5]), is set to 1 when an attempt is made to write to the spi t ransmit shift re gister (spi_tsr) while data transfer occurs. clearing the wcol bit is performed by reading spi_sr with the wcol bit set. spi baud rate generator the spi s baud rate generator creates a lo wer frequenc y clock from the high-frequenc y system clock. the baud rate generator output is used as the clock source by the spi. baud rate generator functional description the spi s baud rate generator consists of a 16-bit do wncounter , tw o 8-bit re gisters, and associated decoding logic. the baud rate generator s initial v alue is de? ned by the tw o brg di visor latch re gisters, {spi_brg_h, spi_brg_l}. at the rising edge of each system clock, the brg decrements until it reaches the v alue 0001h . on the ne xt system clock rising edge, the brg reloads the initial v alue from {spi_brg_h, spi_brg_l) and outputs a pulse to indicate the end-of-count. calculate the spi data rate with the follo w - ing equation: upon reset , the 16-bit brg di visor v alue resets to 0002h . when the spi is operating as a master , the brg di visor v alue must be set to a v alue of 0003h or greater . when the spi is operating as a sla v e, the brg di visor v alue must be set to a v alue of 0004h or greater . a softw are write to either the lo w- or high-byte re gisters for the brg di visor latch causes both the lo w and high bytes to load into the brg counter , and causes the count to restart. data transfer procedure with spi configured as the master 1. load the spi baud rate generator re gisters, spi_brg_h and spi_brg_l. 2. external de vice must deassert the ss pin if currently asserted. 3. load the spi control re gister , spi_ctl. spi data rate (bits/s) = system clock frequency 2 x spi baud rate generator divisor
ps015309-1004 preliminary serial peripheral interface ez80f92/ez80f93 product specification 135 4. assert the en able pin of the sla v e de vice using a gpio pin. 5. load the spi t ransmit shift re gister , spi_tsr. 6. when the spi data transfer is complete, deassert the en able pin of the sla v e de vice. data transfer procedure with spi configured as a slave 1. load the spi baud rate generator re gisters, spi_brg_h and spi_brg_l. 2. load the spi t ransmit shift re gister , spi_tsr. this load cannot occur while the spi sla v e is currently recei ving data. 3. w ait for the e xternal spi master de vice to initiate the data transfer by asserting ss . spi registers there are six re gisters in the serial peripheral interf ace which pro vide control, status, and data storage functions. the spi re gisters are described in the follo wing paragraphs. spi baud rate generator registerslow byte and high byte these re gisters hold the lo w and high bytes of the 16-bit di visor count loaded by the pro - cessor for baud rate generation. the 16-bit clock di visor v alue is returned by {spi_brg_h, spi_brg_l}. upon reset , the 16-bit brg di visor v alue resets to 0002h . when con? gured as a master , the 16-bit di visor v alue must be between 0003h a nd ffffh , inclusi v e. when con? gured as a sla v e, the 16-bit di visor v alue must be between 0004h and ffffh , inclusi v e. a write to either the lo w or high byte re gisters for the brg di visor latch causes both bytes to be loaded into the brg counter and the count restarted. see t ables 74 and 75 . t able 74. spi baud rate generator registerlow byt e (s pi_brg_l = 00b8h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 1 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] spi_brg_l 00hC ffh these bits represent the low byte of the 16-bit baud rate generator divider value. the complete brg divisor value is returned by {spi_brg_h, spi_brg_l}.
ps015309-1004 preliminary serial peripheral interface ez80f92/ez80f93 product specification 136
ps015309-1004 preliminary serial peripheral interface ez80f92/ez80f93 product specification 137 spi control register this re gister is used to control and setup the serial peripheral interf ace. the spi should be disabled prior to making an y changes to cpha or cpol. see t able 76 . t able 75. spi baud rate generator registerhigh byt e (s pi_brg_h = 00b9h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] spi_brg_h 00hC ffh these bits represent the high byte of the 16-bit baud rate generator divider value. the complete brg divisor value is returned by {spi_brg_h, spi_brg_l}. t able 76. spi control registe r (s pi_ctl = 00bah ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 1 0 0 cpu access r/w r r/w r/w r/w r/w r r note: r = read only; r/w = read/write. bit position v alue description 7 irq_en 0 spi system interrupt is disabled. 1 spi system interrupt is enabled. 6 0 reserved. 5 spi_en 0 spi is disabled. 1 spi is enabled. 4 master_en 0 when enabled, the spi operates as a slave. 1 when enabled, the spi operates as a master. 3 cpol 0 master sck pin idles in a low (0) state. 1 master sck pin idles in a high (1) state.
ps015309-1004 preliminary serial peripheral interface ez80f92/ez80f93 product specification 138 spi status register the spi status read only re gister returns the status of data transmitted using the serial peripheral interf ace. reading the spi_sr re gister clears bits 7, 6, and 4 to a logical 0. see t able 77 . 2 cpha 0 ss must go high after transfer of every byte of data. 1 ss can remain low to transfer any number of data bytes. [1:0] 00 reserved. t able 77. spi status registe r (s pi_sr = 00bbh ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description 7 spif 0 spi data transfer is not finished. 1 spi data transfer is finished. if enabled, an interrupt is generated. this bit flag is cleared to 0 by a read of the spi_sr register. 6 wcol 0 an spi write collision is not detected. 1 an spi write collision is detected. this bit flag is cleared to 0 by a read of the spi_sr registers. 5 0 reserved. 4 modf 0 a mode fault ( multimaster conflict) is not detected. 1 a mode fault (multimaster conflict) is detected. this bit flag is cleared to 0 by a read of the spi_sr register. [3:0] 0000 reserved. bit position v alue description
ps015309-1004 preliminary serial peripheral interface ez80f92/ez80f93 product specification 139 spi t ransmit shift register the spi t ransmit shift re gister (spi_tsr) is used by the spi master to transmit data onto the spi serial b us to the sla v e de vice. a write to the spi_tsr re gister places data directly into the shift re gister for transmission. a write to this re gister within an spi de vice con? g - ured as a master initiates transmission of the byte of the data loaded into the re gister . at the completion of transmitting a byte of data, the spif status bit (spi_sr[7]) is set to 1 in both the master and sla v e de vices. the spi t ransmit shift write only re gister shares the same address space as the spi recei v e buf fer read only re gister . see t able 78 . spi receive buffer register the spi recei v e buf fer re gister (spi_rbr) is used by the spi sla v e to recei v e data from the serial b us. the spif bit must be cleared prior to a second transfer of data from the shift re gister or an o v errun condition e xists. in cases of o v errun the byte that caused the o v errun is lost. the spi recei v e buf fer read only re gister shares the same address space as the spi t ransmit shift write only re gister . see t able 79 . t able 78. spi t ransmit shift registe r (s pi_tsr = 00bch ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: w = write only. bit position v alue description [7:0] tx_data 00hC ffh spi transmit data. t able 79. spi receive buffer registe r (s pi_rbr = 00bch ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] rx_data 00hC ffh spi received data.
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 140 i 2c serial i/o interface i 2 c general characteristics the i 2 c serial i/o b us is a tw o-wire communication interf ace that can operate in four modes: ? master transmit ? master receive ? slave transmit ? slave receive the i 2 c interf ace consists of the serial clock ( scl) and the serial data ( sd a). both sd a and scl are bidirectional lines, connected to a positi v e supply v oltage via an e xternal pull-up resistor . when the b us is free, both lines are high. the output stages of de vices connected to the b us must be con? gured as open-drain outputs. data on the i 2 c b us can be transferred at a rate of up to 100 kbps in standard mode, or up to 400 kbps in f ast mode. one clock pulse is generated for each data bit transferred. clocking overview if another de vice on the i 2 c b us dri v es the clock line when the i 2 c is in master mode, the i 2 c synchronizes its clock to the i 2 c b us clock. the high period of the clock is deter - mined by the de vice that generates the shortest high clock period. the lo w period of the clock is determined by the de vice that generates the longest lo w clock period. a sla v e may stretch the lo w period of the clock to slo w do wn the b us master . the lo w period may also be stretched for handshaking purposes. this can be done after each bit transfer or each byte transfer . the i 2 c stretches the clock after each byte transfer until the iflg bit in the i2c_ctl re gister is cleared. bus arbitration overview in master mode, the i 2 c checks that each transmitted logic 1 appears on the i 2 c b us as a logic 1. if another de vice on the b us o v errules and pulls the sd a signal lo w , arbitration is lost. if arbitration is lost during the transmission of a data byte or a not-ackno wledge bit, the i 2 c returns to the idle state. if arbitration is lost during the transmission of an address, the i 2 c switches to sla ve mode so that it can recognize its o wn sla v e address or the general call address.
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 141 data v alidity the data on the sd a line must be stable during the high period of the clock. the high or lo w state of the data line can only change when the clock signal on the scl line is lo w as illustrated in figure 31 . st art and st op conditions w ithin the i 2 c b us protocol, unique situations arise which are de? ned as st ar t and st op conditions. see figure 32 . a high-to-lo w transition on the sd a line while scl is high indicates a start c ondition. a lo w-to-high transition on the sd a line while scl is high de? nes a st op condition. st ar t and st op conditions are al w ays generated by the master . the b us is considered to be b usy after the start condition. the b us is considered to be free a de? ned time after the stop condition. figure 31. i 2 c clock and data relationship figure 32. st art and st op conditions in i 2 c protocol sda signal scl signal data line stable data valid change of data allowed sda signal start condition stop condition scl signal sp
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 142 transferring data byte format ev ery character transferred on the sd a line must be a single 8-bit byte. the number of bytes that can be transmitted per transfer is unrestricted. each byte must be follo wed by an ackno wledge (a ck) 1 . data is transferred with the most-signi? cant bit ( msb) ? rst. see figure 33 . a recei v er can hold the scl line lo w to force the transmitter into a w ait state. data transfer then continues when the recei v er is ready for another byte of data and releases scl. acknowledge data transfer with an a ck function is oblig atory . the a ck-related clock pulse is gener - ated by the master . the transmitter releases the sd a line (high) during the a ck clock pulse. the recei v er must pull do wn the sd a line during the a ck clock pulse so that it remains stable lo w during the high period of this clock pulse. see figure 34 . a recei v er that is addressed is obliged to generate an a ck after each byte is recei v ed. when a sla v e-recei v er doesn't ackno wledge the sla v e address (for e xample, unable to recei v e because it's performing some real-time function), the data line must be left high by the sla v e. the master then generates a st op condition to abort the transfer . if a sla v e-recei v er ackno wledges the sla v e address, b ut cannot recei v e an y more data bytes, the master must abort the transfer . the abort is indicated by the sla v e generating the not ackno wledge ( n a ck) on the ? rst byte to follo w . the sla v e lea v es the data line high and the master generates the st op condition. if a master -recei v er is in v olv ed in a transfer , it must signal the end of data to the sla v e- transmitter by not generating an a ck on the ? nal byte that is clock ed out of the sla v e. the 1. ack is defined as a general acknowledge bit. by contrast, the i 2 c acknowledge bit is represented as aak, bit 2 of the i 2 c control register, which identifies which ack signal to transmit. see table 89 on page 156 . figure 33. i 2 c frame structure sda signal scl signal start condition clock line held low by receiver stop condition s p acknowledge from receiver msb ack 9 1 9 12 8 acknowledge from receiver
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 143 sla v e-transmitter must release the data line to allo w the master to generate a st op or a repeated start condition. clock synchronization all masters generate their o wn clocks on the scl line to transfer messages on the i 2 c b us. data is only v alid during the high period of each clock. clock synchronization is performed using the wired and connection of the i 2 c interf aces to the scl line, meaning that a high-to-lo w transition on the scl line causes the rele v ant de vices to start counting from their lo w period. when a de vice clock goes lo w , it holds the scl line in that state until the clock high state is reached. see figure 35 . the lo w-to- high transition of this clock, ho we v er , may not change the state of the scl line if another clock is still within its lo w period. the scl line is held lo w by the de vice with the long - est lo w period. de vices with shorter lo w periods enter a high w ait-state during this time. when all de vices concerned count of f their lo w period, the clock line is released and goes high. there is no dif ference between the de vice clocks and the state of the scl line, and all of the de vices start counting their high periods. the ? rst de vice to complete its high period ag ain pulls the scl line lo w . in this w ay , a synchronized scl clock is generated with its lo w period determined by the de vice with the longest clock lo w period, and its high period determined by the one with the shortest clock high period. figure 34. i 2 c acknowledge data output by transmitter data output by receiver scl signal from master start condition s msb 1 clock pulse for acknowledge 9 12 8
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 144 arbitration a master may start a transfer only if the b us is free. t w o or more masters may generate a start condition within the minimum hold time of the st ar t condition which results in a de? ned start condition to the b us. arbitration tak es place on the sd a line, while the scl line is at the high le v el, in such a w ay that the master which transmits a high le v el, while another master is transmitting a lo w le v el switches of f its data output stage because the le v el on the b us doesn't correspond to its o wn le v el. arbitration can continue for man y bits. its ? rst stage is comparison of the address bits. if the masters are each trying to address the same de vice, arbitration continues with compar - ison of the data. because address and data information about t he i 2 c b us is used for arbi - tration, no information is lost during this process. a master which loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration. if a master also incorporates a sla v e function and it loses arbitration during the addressing stage, it's possible that the winning master is trying to address it. the losing master must switch o v er immediately to its sla v e-recei v er mode. figure 35 illustrates the arbitration procedure for tw o masters. of course, more may be in v olv ed (depending on ho w man y masters are connected to the b us). the moment there is a dif ference between the internal data le v el of the master generating d a t a 1 and the actual le v el on the sd a line, its data output is switched of f, which means that a high output le v el is then connected to the b us. as a result, the data transfer initiated by the winning master is not af fected. because con - trol of the i 2 c b us is decided solely on the address and data sent by competing masters, there is no central master , nor an y order of priority on the b us. special attention must be paid if, during a serial transfer , the arbitration procedure is still in progress at the moment when a repeated st ar t condition or a st op condition is trans - mitted to the i 2 c b us. if it is possible for such a situation to occur , the masters in v olv ed must send this repeated start condition or st op condition at the same position in the format frame. in other w ords, arbitration is not allo wed between: ? a repeated st ar t condition and a data bit figure 35. clock synchronization in i 2 c protocol clk1 signal clk2 signal scl signal counter reset wait state start counting high period
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 145 ? a st op condition and a data bit ? a repeated st ar t condition and a st op condition clock synchronization for handshake the clock synchronizing mechanism can function as a handshak e, enabling recei v ers to cope with f ast data transfers, on either a byte or bit le v el. the byte le v el allo ws a de vice to recei v e a byte of data at a f ast rate, b ut allo ws the de vice more time to store the recei v ed byte or to prepare another byte for transmission. sla v es hold the scl line lo w after recep - tion and ackno wledge the byte, forcing the master into a w ait state until the sla v e is ready for the ne xt byte transfer in a handshak e procedure. operating modes master t ransmit in master transmit mode, the i 2 c transmits a number of bytes to a sla v e recei v er . enter master transmit mode by setting the st a bit in the i2c_ctl re gister to 1. the i 2 c then tests the i 2 c b us and transmits a st ar t condition when the b us is free. when a st ar t condition is transmitted, the iflg bit is 1 and the status code in the i2c_sr re gister is 08h . before this interrupt is serviced, the i2c_dr re gister must be loaded with either a 7-bit sla v e address or the ? rst part of a 10-bit sla v e address, with the lsb cleared to 0 to specify transmit mode. the iflg bit should no w be cleared to 0 to prompt the transfer to continue. after the 7-bit sla v e address (or the ? rst part of a 10-bit address) plus the write bit are transmitted, the iflg is set ag ain. a number of status codes are possible in the i2c_sr re gister . see t able 80 .
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 146 if 10-bit addressing is being used, then the status code is 18h or 20h after the ? rst part of a 10-bit address plus the write bit are successfully transmitted. after this interrupt is serviced and the second part of the 10-bit address is transmitted, the i2c_sr re gister contains one of the codes in t able 81 . t able 80. i 2 c master t ransmit status codes code i 2 c state microcontroller response next i 2 c action 18h addr+w transmitted, ack received for a 7-bit address: write byte to data, clear iflg transmit data byte, receive ack or set sta, clear iflg transmit repeated start or set stp, clear iflg transmit stop or set sta & stp, clear iflg transmit stop then start for a 10-bit address: write extended address byte to data, clear iflg transmit extended address byte 20h addr+w transmitted, ack not received same as code 18h same as code 18h 38h arbitration lost clear iflg return to idle or set sta, clear iflg transmit start when bus is free 68h arbitration lost, +w received, ack transmitted clear iflg, aak = 0 receive data byte, transmit nack or clear iflg, aak = 1 receive data byte, transmit ack 78h arbitration lost, general call addr received, ack transmitted same as code 68h same as code 68h b0h arbitration lost, sla+r received, ack transmitted write byte to data, clear iflg, clear aak = 0 transmit last byte, receive ack or write byte to data, clear iflg, set aak = 1 transmit data byte, receive ack w = write bit; that is, the lsb is cleared to 0.
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 147 if a repeated start condition is transmitted, the status code is 10h instead of 08h . after each data byte is transmitted, the iflg is 1 and one of the status codes listed in t able 82 is in the i2c_sr re gister . t able 81. i 2 c 10-bit master t ransmit status codes code i 2 c state microcontroller response next i 2 c action 38h arbitration lost clear iflg return to idle or set sta, clear iflg transmit start when bus free 68h arbitration lost, sla+w received, ack transmitted clear iflg, clear aak = 0 receive data byte, transmit nack or clear iflg, set aak = 1 receive data byte, transmit ack b0h arbitration lost, sla+r received, ack transmitted write byte to data, clear iflg, clear aak = 0 transmit last byte, receive ack or write byte to data, clear iflg, set aak = 1 transmit data byte, receive ack d0h second address byte + w transmitted, ack received write byte to data, clear iflg transmit data byte, receive ack or set sta, clear iflg transmit repeated start or set stp, clear iflg transmit stop or set sta & stp, clear iflg transmit stop then start d8h second address byte + w transmitted, ack not received same as code d0h same as code d0h t able 82. i 2 c master t ransmit status codes for data bytes code i 2 c state microcontroller response next i 2 c action 28h data byte transmitted, ack received write byte to data, clear iflg transmit data byte, receive ack or set sta, clear iflg transmit repeated start or set stp, clear iflg transmit stop or set sta & stp, clear iflg transmit start then stop
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 148 when all bytes are transmitted, the microcontroller should write a 1 to the stp bit in the i2c_ctl re gister . the i 2 c then transmits a st op condition, clears the stp bit and returns to the idle state. master receive in master receive mode, the i 2 c recei v es a number of bytes from a sla v e transmitter . after the start condition is transmitted, the iflg bit is 1 and the status code 08h is loaded in the i2c_sr re gister . the i2c_dr re gister should be loaded with the sla v e address (or the ? rst part of a 10-bit sla v e address), with the lsb set to 1 to signify a read. the iflg bit should be cleared to 0 as a prompt for the transfer to continue. when the 7-bit sla v e address (or the ? rst part of a 10-bit address) and the read bit are transmitted, the iflg bit is set and one of the status codes listed in t able 83 is in the i2c_sr re gister . 30h data byte transmitted, ack not received same as code 28h same as code 28h 38h arbitration lost clear iflg return to idle or set sta, clear iflg transmit start when bus free t able 83. i 2 c master receive status codes code i 2 c state microcontroller response next i 2 c action 40h addr + r transmitted, ack received for a 7-bit address, clear iflg, aak = 0 receive data byte, transmit nack or clear iflg, aak = 1 receive data byte, transmit ack for a 10-bit address write extended address byte to data, clear iflg transmit extended address byte r = read bit; that is, the lsb is set to 1. t able 82. i 2 c master t ransmit status codes for data bytes (continued) code i 2 c state microcontroller response next i 2 c action
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 149 if 10-bit addressing is being used, the sla v e is ? rst addressed using the full 10-bit address plus the write bit. the master then issues a restart follo wed by the ? rst part of the 10-bit address ag ain, b ut with the read bit. the status code then becomes 40h or 48h . it is the responsibility of the sla v e to remember that it had been selected prior to the restart. if a repeated start condition is recei v ed, the status code is 10h instead of 08h . after each data byte is recei v ed, the iflg is set and one of the status codes listed in t able 84 is in the i2c_sr re gister . 48h addr + r transmitted, ack not received for a 7-bit address: set sta, clear iflg transmit repeated start or set stp, clear iflg transmit stop or set sta & stp, clear iflg transmit stop then start for a 10-bit address: write extended address byte to data, clear iflg transmit extended address byte 38h arbitration lost clear iflg return to idle or set sta, clear iflg transmit start when bus is free 68h arbitration lost, sla+w received, ack transmitted clear iflg, clear aak = 0 receive data byte, transmit nack or clear iflg, set aak = 1 receive data byte, transmit ack 78h arbitration lost, general call addr received, ack transmitted same as code 68h same as code 68h b0h arbitration lost, sla+r received, ack transmitted write byte to data, clear iflg, clear aak = 0 transmit last byte, receive ack or write byte to data, clear iflg, set aak = 1 transmit data byte, receive ack t able 83. i 2 c master receive status codes code i 2 c state microcontroller response next i 2 c action r = read bit; that is, the lsb is set to 1.
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 150 when all bytes are recei v ed, a n a ck should be sent, then the microcontroller should write a 1 to the stp bit in the i2c_ctl re gister . the i 2 c then transmits a st op condition, clears the stp bit and returns to the idle state. slave t ransmit in slave transmit mode, a number of bytes are transmitted to a master recei v er . the i 2 c enters slave transmit mode when it recei v es its o wn sla v e address and a read bit after a start condition. the i 2 c then transmits an ackno wledge bit (if the aak bit is set to 1) and sets the iflg bit in the i2c_ctl re gister and the i2c_sr re gister con - tains the status code a8h . when i 2 c contains a 10-bit sla v e address (signi? ed by f0h?7h in the i2c_sar re gister), it transmits an ackno wledge after the ? rst address byte is recei v ed after a restart. an interrupt is generated, iflg is set b ut the status does not change. no second address byte is sent by the master . it is up to the sla v e to remember it had been selected prior to the restart. i 2 c goes from master mode to slave transmit mode when arbitration is lost dur - ing the transmission of an address, and the sla v e address and read bit are recei v ed. this action is represented by the status code b0h in the i2c_sr re gister . the data byte to be transmitted is loaded into the i2c_dr re gister and the iflg bit cleared. after the i 2 c transmits the byte and recei v es an ackno wledge, the iflg bit is set and the i2c_sr re gister contains b8h . when the ? nal byte to be transmitted is loaded into the i2c_dr re gister , the aak bit is cleared when the iflg is cleared. after the ? nal byte t able 84. i 2 c master receive status codes for data bytes code i 2 c state microcontroller response next i 2 c action 50h data byte received, ack transmitted read data, clear iflg, clear aak = 0 receive data byte, transmit nack or read data, clear iflg, set aak = 1 receive data byte, transmit ack 58h data byte received, nack transmitted read data, set sta, clear iflg transmit repeated start or read data, set stp, clear iflg transmit stop or read data, set sta & stp, clear iflg transmit stop then start 38h arbitration lost in nack bit same as master transmit same as master transmit note:
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 151 is transmitted, the iflg is set and the i2c_sr re gister contains c8h a nd the i 2 c returns to the idle state. the aak bit must be set to 1 before reentering slave mode. if no ackno wledge is recei v ed after transmitting a byte, the iflg is set and the i2c_sr re gister contains c0h . the i 2 c then returns to the idle state. if a st op condition is detected after an ackno wledge bit, the i 2 c returns to the idle state. slave receive in slave receive mode, a number of data bytes are recei v ed from a master transmit - ter . the i 2 c enters slave receive mode when it recei v es its o wn sla v e address and a write bit ( lsb = 0) after a start condition. the i 2 c transmits an ackno wledge bit and sets the iflg bit in the i2c_ctl re gister and the i2c_sr re gister contains the status code 60h . the i 2 c also enters slave receive mode when it recei v es the general call address 00h (if the gce bit in the i2c_sar re gister is set). the status code is then 70h . when the i 2 c contains a 10-bit sla v e address (signi? ed by f0h?7h in the i2c_sar re gister), it transmits an ackno wledge after the ? rst address byte is recei v ed b ut no interrupt is generated. iflg is not set and the status does not change. the i 2 c generates an interrupt only after the second address byte is recei v ed. the i 2 c sets the iflg bit and loads the status code as described abo v e. i 2 c goes from master mode to slave receive mode when arbitration is lost during the transmission of an address, and the sla v e address and write bit (or the general call address if the cge bit in the i2c_sar re gister is set to 1) are recei v ed. the status code in the i2c_sr re gister is 68h if the sla v e address is recei v ed or 78h if the general call address is recei v ed. the iflg bit must be cleared to 0 to allo w data transfer to continue. if the aak bit in the i2c_ctl register is set to 1 then an ackno wledge bit (lo w le v el on sd a) is transmitted and the iflg bit is set after each byte is recei v ed. the i2c_sr re gis - ter contains the status code 80h or 90h if slave receive mode is entered with the general call address. the recei v ed data byte can be read from the i2c_dr re gister and the iflg bit must be cleared to allo w the transfer to continue. if a st op condition or a repeated start condition is detected after the ackno wledge bit, the iflg bit is set and the i2c_sr re gister contains status code a0h . if the aak bit is cleared to 0 during a transfer , the i 2 c transmits a not-ackno wledge bit (high le v el on sd a) after the ne xt byte is recei v ed, and set the iflg bit. the i2c_sr re g - ister contains the status code 88h or 98h if slave receive mode is entered with the general call address. the i 2 c returns to the idle state when the iflg bit is cleared to 0. note:
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 152 i 2 c registers addressing the processor interf ace pro vides access to six 8-bit re gisters: four read/write re gisters, one read only re gister and tw o write only re gisters, as indicated in t able 85 . resetting the i 2 c registers hardware reset. when the i 2 c is reset by a hardw are reset of the ez80f92 de vice, the i2c_sar , i2c_xsar , i2c_dr and i2c_ctl re gisters are cleared to 00h ; while the i2c_sr re gister is set to f8h . software reset . perform a softw are reset by writing an y v alue to the i 2 c softw are reset re gister ( i2c_srr ). a softw are reset sets the i 2 c back to idle and the stp , st a, and iflg bits of the i2c_ctl re gister to 0. i 2 c slave address register the i2c_sar re gister pro vides the 7-bit address of the i 2 c when in slave mode and allo ws 10-bit addressing in conjunction with the i2c_xsar re gister . i2c_sar[7:1] = sla[6:0] is the 7-bit address of the i 2 c when in 7-bit slave mode. when the i 2 c recei v es this address after a start condition, it enters slave mode. i2c_sar[7] corresponds to the ? rst bit recei v ed from the i 2 c b us. when the re gister recei v es an address starting with f7h to f0h (i2c_sar[7:3] = 11110b), the i 2 c recognizes that a 10-bit sla v e addressing mode is being selected. the i 2 c sends an a ck after recei ving the i2c_sar byte (the de vice does not generate an interrupt at this point). after the ne xt byte of the address (i2c_xsar) is recei v ed, the i 2 c generates an interrupt and goes into slave mode. then i 2c_sar[2:1] are used as the upper 2 bits for the 10-bit e xtended address. the full 10-bit address is supplied by {i2c_sar[2:1], i2c_xsar[7:0]}. see t able 86 . t able 85. i 2 c register descriptions register description i2c_sar slave address register i2c_xsar extended slave address register i2c_dr data byte register i2c_ctl control register i2c_sr status register (read only) i2c_ccr clock control register (write only) i2c_srr software reset register (write only)
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 153 i 2 c extended slave address register the i2c_xsar re gister is used in conjunction with the i2c_sar re gister to pro vide 10- bit addressing of the i 2 c when in slave mode. the i2c_sar v alue forms the lo wer 8 bits of the 10-bit sla v e address. the full 10-bit address is supplied by {i2c_sar[2:1], i2c_xsar[7:0]}. when the re gister recei v es an address starting with f7h to f0h (i2c_sar[7:3] = 11110b), the i 2 c recognizes that a 10-bit sla v e addressing mode is being selected. the i 2 c sends an a ck after recei ving the i2c_xsar byte (the de vice does not generate an interrupt at this point). after the ne xt byte of the address (i2c_xsar) is recei v ed, the i 2 c generates an interrupt and goes into sla ve mode. then i 2c_sar[2:1] are used as the upper 2 bits for the 10-bit e xtended address. the full 10-bit address is supplied by {i2c_sar[2:1], i2c_xsar[7:0]}. see t able 87 . t able 86. i 2 c slave address register s (i 2c_sar = 00c8h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:1] sla 00hC 7fh 7-bit slave address or upper 2 bits,i2c_sar[2:1], of address when operating in 10-bit mode. 0 gce 0 i 2 c not enabled to recognize the general call address. 1 i 2 c enabled to recognize the general call address.
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 154 i 2 c data register this re gister contains the data byte/sla v e address to be transmitted or the data byte just recei v ed. in transmit mode, the most-signi? cant bit of the byte is transmitted ? rst. in recei v e mode, the ? rst bit recei v ed is placed in the most-signi? cant bit of the re gister . after each byte is transmitted, the i2c_dr re gister contains the byte that is present on the b us in case a lost arbitration e v ent occurs. see t able 88 . i 2 c control register the i2c_ctl re gister is a control re gister that is used to control the interrupts and the master sla v e relationships on the i 2 c b us. when the interrupt enable bit (ien) is set to 1, the interrupt line goes high when the iflg is set to 1. when ien is cleared to 0, the interrupt line al w ays remains lo w . when the bus enable bit ( en ab) is set to 0, the i 2 c b us inputs sclx and sd ax are ignored and the i 2 c module does not respond to an y address on the b us. when en ab is t able 87. i 2 c extended slave address register s (i 2c_xsar = 00c9h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] slax 00hC ffh least-significant 8 bits of the 10-bit extended slave address. t able 88. i 2 c data register s (i 2c_dr = 00cah ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] data 00hC ffh i 2 c data byte.
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 155 set to 1, the i 2 c responds to calls to its sla v e address and to the general call address if the gce bit (i2c_sar[0]) is set to 1. when the master mode start bit ( st a) is set to 1, the i 2 c enters master mode and sends a start condition on the b us when the b us is free. if the st a bit is set to 1 when the i 2 c module is already in master mode and one or more bytes are transmitted, then a repeated st ar t condition is sent. if the st a bit is set to 1 when the i 2 c block is being accessed in sla ve mode, the i 2 c completes the data transfer in sla ve mode and then enters master mode when the b us is released. the st a bit is automatically cleared after a st ar t condition is set. writing a 0 to this bit produces no ef fect. if the master mode stop bit ( stp) is set to 1 in master mode, a st op condition is transmitted on the i 2 c b us. if the stp bit is set to 1 in sla v e mo v e, the i 2 c module operates as if a st op condition is recei v ed, b ut no st op condition is transmitted. if both st a and stp bits are set, the i 2 c block ? rst transmits the st op condition (if in master mode) and then transmit the st ar t condition. the stp bit is cleared automatically . writing a 0 to this bit produces no ef fect. the i 2 c interrupt flag (iflg) is set to 1 automatically when an y of 30 of the possible 31 i 2 c states is entered. the only state that does not set the iflg bit is state f8h. if iflg is set to 1 and the ien bit is also set, an interrupt is generated. when iflg is set by the i 2 c , the lo w period of the i 2 c b us clock line is stretched and the data transfer is suspended. when a 0 is written to iflg, the interrupt is cleared and the i 2 c clock line is released. when the i 2 c ackno wledge bit ( aak) is set to 1, an ackno wledge is sent during the ackno wledge clock pulse on the i 2 c b us if: ? either the whole of a 7-bit sla v e address or the ? rst or second byte of a 10-bit sla v e address is recei v ed ? the general call address is recei v ed and the general call enable bit in i2c_sar is set to 1 ? a data byte is recei v ed while in master or sla ve modes when aak is cleared to 0, a n a ck is sent when a data byte is recei v ed in master or sla ve mode. if aak is cleared to 0 in the sla v e t ransmitter mode, the byte in the i2c_dr re gister is assumed to be the ? nal byte. after this byte is transmitted, the i 2 c block enter states c8h , then returns to the idle state. the i 2 c module does not respond to its sla v e address unless aak is set. see t able 89 .
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 156 t able 89. i 2 c control register s (i 2c_ctl = 00cbh ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r r note: r/w = read/write; r = read only. bit position v alue description 7 ien 0 i 2 c interrupt is disabled. 1 i 2 c interrupt is enabled. 6 enab 0 the i 2 c bus (scl/sda) is disabled and all inputs are ignored. 1 the i 2 c bus (scl/sda) is enabled. 5 sta 0 master mode start condition is sent. 1 master mode start-transmit start condition on the bus. 4 stp 0 master mode stop condition is sent. 1 master mode stop-transmit stop condition on the bus. 3 iflg 0 i 2 c interrupt flag is not set. 1 i 2 c interrupt flag is set. 2 aak 0 not acknowledge. 1 acknowledge. [1:0] 00 reserved.
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 157 i 2 c status register the i2c_sr re gister is a read only re gister that contains a 5-bit status code in the ? v e most-signi? cant bits: the three least-signi? cant bits are al w ays 0. the read only i2c_sr re gisters share the same i/o addresses as the write only i2c_ccr re gisters. see t able 90 . there are 29 possible status codes, as listed in t able 91 . when the i2c_sr re gister con - tains the status code f8h , no rele v ant status information is a v ailable, no interrupt is gener - ated and the iflg bit in the i2c_ctl re gister is not set. all other status codes correspond to a de? ned state of the i 2 c . when each of these states is entered, the corresponding status code appears in this re gister and the iflg bit in the i2c_ctl re gister is set. when the iflg bit is cleared, the status code returns to f8h . t able 90. i 2 c status register s (i 2c_sr = 00cch ) bit 7 6 5 4 3 2 1 0 reset 1 1 1 1 1 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:3] stat 00000C 11111 5-bit i 2 c status code. [2:0] 000 reserved. t able 91. i 2 c status codes code status 00h bus error 08h start condition transmitted 10h repeated start condition transmitted 18h address and write bit transmitted, ack received 20h address and write bit transmitted, ack not received 28h data byte transmitted in master mode, ack received 30h data byte transmitted in master mode, ack not received 38h arbitration lost in address or data byte 40h address and read bit transmitted, ack received
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 158 if an ille g al condition occurs on the i 2 c b us, the b us error state is entered (status code 00h ). t o reco v er from this state, the stp bit in the i2c_ctl re gister must be set and the iflg bit cleared. the i 2 c then returns to the idle state. no st op condition is transmitted on the i 2 c b us. the stp and st a bits may be set to 1 at the same time to reco v er from the b us error . the i 2 c then sends a st ar t condition. 48h address and read bit transmitted, ack not received 50h data byte received in master mode, ack transmitted 58h data byte received in master mode, nack transmitted 60h slave address and write bit received, ack transmitted 68h arbitration lost in address as master, slave address and write bit received, ack transmitted 70h general call address received, ack transmitted 78h arbitration lost in address as master, general call address received, ack transmitted 80h data byte received after slave address received, ack transmitted 88h data byte received after slave address received, nack transmitted 90h data byte received after general call received, ack transmitted 98h data byte received after general call received, nack transmitted a0h stop or repeated start condition received in slave mode a8h slave address and read bit received, ack transmitted b0h arbitration lost in address as master, slave address and read bit received, ack transmitted b8h data byte transmitted in slave mode, ack received c0h data byte transmitted in slave mode, ack not received c8h last byte transmitted in slave mode, ack received d0h second address byte and write bit transmitted, ack received d8h second address byte and write bit transmitted, ack not received f8h no relevant status information, iflg = 0 t able 91. i 2 c status codes (continued) code status note:
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 159 i 2 c clock control register the i2c_ccr re gister is a write only re gister . the se v en lsbs control the frequenc y at which the i 2 c b us is sampled and the frequenc y of the i 2 c clock line ( scl) when the i 2 c is in master mode. the write only i2c_ccr re gisters share the same i/o addresses as the read only i2c_sr re gisters. see t able 92 . the i 2 c clocks are deri v ed from the cpu system clock. the frequenc y of the cpu system clock is f sck . the i 2 c b us is sampled by the i 2 c block at the frequenc y f samp supplied by: in master mode, the i 2 c clock output frequenc y on scl ( f scl ) is supplied by: the use of tw o separately-programmable di viders allo ws the master mode output fre - quenc y to be set independently of the frequenc y at which the i 2 c b us is sampled. this fea - ture is particularly useful in multimaster systems because the frequenc y at which the i 2 c b us is sampled must be at least 10 times the frequenc y of the f astest master on the b us to ensure that st ar t and st op conditions are al w ays detected. by using tw o programma - ble clock di vider stages, a high sampling frequenc y can be ensured while allo wing the master mode output to be set to a lo wer frequenc y . t able 92. i 2 c clock control register s (i 2c_ccr = 00cch ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = read only. bit position v alue description 7 0 reserved. [6:3] m 0000C 1111 i 2 c clock divider scalar value. [2:0] n 000C 111 i 2 c clock divider exponent. f samp = f sclk 2 n f scl = f sclk 10 ? (m + 1)(2) n
ps015309-1004 preliminary i 2 c serial i/o interface ez80f92/ez80f93 product specification 160 bus clock speed the i 2 c b us is de? ned for b us clock speeds up to 100 kbps (400 kbps in f ast mode). t o ensure correct detection of st ar t and st op conditions on the b us, the i 2 c must sam - ple the i 2 c b us at least ten times f aster than the b us clock speed of the f astest master on the b us. the sampling frequenc y should therefore be at least 1 mhz (4 mhz in f ast mode) to guarantee correct operation with other b us masters. the i 2 c s ampling frequenc y is determined by the frequenc y of the cpu system clock and the v alue in the i2c_ccr bits 2 to 0. the b us clock speed generated by the i 2 c in mas - ter mode is determined by the frequenc y of the input clock and the v alues in i2c_ccr[2:0] and i2c_ccr[6:3]. i 2 c software reset register the i2c_srr re gister is a write only re gister . writing an y v alue to this re gister performs a softw are reset of the i 2 c module. see t able 93 . t able 93. i 2 c software reset registe r (i 2c_srr = 00cdh ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: w = write only. bit position v alue description [7:0] srr 00hC ffh writing any value to this register performs a software reset of the i 2 c module.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 161 zilog debug interface introduction the zilog deb ug interf ace ( zdi) pro vides a b uilt-in deb ugging interf ace to the ez80 ? cpu. zdi pro vides basic in-circuit emulation features including: ? examining and modifying internal re gisters ? examining and modifying memory ? starting and stopping the user program ? setting program and data break points ? single-stepping the user program ? ex ecuting user -supplied instructions ? deb ugging the ? nal product with the inclusion of one small connector ? do wnloading code into sram ? c source-le v el deb ugging using zilog de v eloper studio ( zds ii ) the abo v e features are b uilt into the silicon. control is pro vided via a tw o-wire interf ace that is connected to the zp ak ii deb ug interf ace t ool. figure 36 illustrates a typical setup using a a tar get board, zp ak ii , and the host pc running zilog de v eloper studio. refer to the zilog website for more information about zp ak ii and zds ii . zdi allo ws reading and writing of most internal re gisters without disturbing the state of the machine. reads and writes to memory may occur as f ast as the zdi can do wnload and upload data, with a maximum frequenc y of one-half the cpu system clock frequenc y . figure 36. t ypical zdi debug setup zilog developer studio zpak emulator ez80 product t arget board c o n n e c t o r
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 162 t able 94 lists the recommended frequencies of the zdi clock in relation to the system clock. zdi-supported protocol zdi supports a bidirectional serial protocol. the protocol de? nes an y de vice that sends data as the tr ansmitter a nd an y recei ving de vice as the r eceiver . the de vice controlling the transfer is the master and the de vice being controlled is the slave . the master al w ays ini - tiates the data transfers and pro vides the clock for both recei v e and transmit operations. the zdi block on the ez80f92 de vice is considered a sla v e in all data transfers. figure 37 illustrates the schematic for b uilding a connector on a tar get board. this connec - tor allo ws the user to connect directly to the zp ak ii deb ugger using a six-pin header . zdi clock and data conventions the tw o pins used for communication with the zdi block are the zdi clock pin ( zcl) and the zdi data pin ( zd a). on the ez80f92 de vice, the zcl pin is shared with the tck pin while the zd a pin is shared with the tdi pin. the zcl and zd a pin functions are t able 94. recommended zdi clock vs. system clock frequency system clock frequency zdi clock frequency 3C10 mhz 1 mhz 8C16 mhz 2 mhz 12C24 mhz 4 mhz 20C50 mhz 8 mhz figure 37. schematic for building a t arget board zp ak ii connector 6-pin target connector 1 3 5 2 4 6 ez80f92 mcu 10 k? 10 k? tck (zcl) tdi (zda) tv dd (target v ) dd
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 163 only a v ailable when the on-chip instrumentation is disabled and the zdi is therefore enabled. f or general data communication, the data v alue on the zda pin can change only when zcl is lo w (0). the only e xception is the zdi st ar t bit, which is indicated by a high-to-lo w transition (f alling edge) on the zda pin while zcl is high. data is shifted into and out of zdi, with the most-signi? cant bit (bit 7) of each byte being ? rst in time, and the least-signi? cant bit (bit 0) last in time. all information is passed between the master and the sla v e in 8-bit (single-byte) units. each byte is transferred with nine clock c ycles: eight to shift the data, and the ninth for internal operations. zdi start condition all zdi commands are preceded by the zdi st ar t signal, which is a high-to-lo w tran - sition of zda when zcl is high. the zdi sla v e on the ez80f92 de vice continually mon - itors the zda a nd zcl lines for the st ar t signal and does not respond to an y command until this condition is met. the master pulls zda lo w , with zcl high, to indicate the be ginning of a data transfer with the zdi block. figures 38 and 39 illustrate a v alid zdi st ar t signal prior to writing and reading data, respecti v ely . a lo w-to-high transition of zda while the zcl is high yields no ef fect. data is shifted in during a write to the zdi block on the rising edge of zcl, as illustrated in figure 38 . data is shifted out during a read from the zdi block on the f alling edge of zcl as illustrated in figure 39 . when an operation is completed, the master stops during the ninth c ycle and holds the zcl signal high. figure 38. zdi w rite t iming zdi data in (write) zdi data in (write) start signal zcl zda
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 164 zdi single-bit byte separator f ollo wing each 8-bit zdi data transfer , a single-bit byte separator is used. t o initiate a ne w zdi command, the single-bit byte separator must be high (logical 1) to allo w for a ne w zdi st ar t command to be sent. f or all other cases, the single-bit byte separator can be either lo w (logical 0) or high (logical 1). when zdi is con? gured to allo w the cpu to accept e xternal b us requests, the single-bit byte separator should be lo w (logical 0) during all zdi commands. this lo w v alue indicates that zdi is still operating and is not ready to relinquish the bus. the cpu does not accept the e xternal b us requests until the single-bit byte separator is a high (logical 1). f or more information about a ccepting b us requests in zdi debug mode, please see the bus requests during zdi deb ug mode section on page 168 . zdi register addressing f ollo wing a st ar t signal the zdi master must output the zdi re gister address. all data transfers with the zdi block use special zdi re gisters. the zdi control re gisters that reside in the zdi re gister address space should not be confused with the ez80f92 de vice peripheral re gisters that reside in the i/o address space. man y locations in the zdi control re gister address space are shared by tw o re gisters, one for read only access and one for write only access. as an e xample, a read from zdi re gister address 00h returns the ez80 product id lo w byte while a write to this same location, 00h , stores the lo w byte of one of the address match v alues used for generating break points. the format for a zdi address is se v en bits of address, follo wed by one bit for read or write control, and completed by a single-bit byte separator . the zdi e x ecutes a read or write operation depending on the state of the r/ w bit (0 = write, 1 = read). if no ne w st ar t command is issued at completion of the read or write operation, the operation figure 39. zdi read t iming zdi data out (read) zdi data out (read) start signal zcl zda
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 165 can be repeated. repeated read or write operations can occur without requiring a resend of the zdi command. t o initiate a ne w zdi command, a st ar t signal must follo w . figure 40 illustrates the timing for address writes to zdi re gisters. zdi write operations zdi single-byte w rite f or single-byte write operations, the address and write control bit are ? rst written to the zdi block. f ollo wing the single-bit byte separator , the data is shifted into the zdi block on the ne xt 8 rising edges of zcl. the master terminates acti vity after 8 clock c ycles. figure 41 illustrates the timing for zdi single-byte write operations. figure 40. zdi address w rite t iming figure 41. zdi single-byte data w rite t iming zdi address byte single-bit byte separator or new zdi start signal start signal 0 = write 1 = read lsb msb zcl s 1 2 3 4567 89 a6 a5 a4 a3 a2 a1 a0 r/w 0/1 zda zdi data byte lsb of zdi address single-bit byte separator lsb of data msb of data end of data or new zdi start signal zcl 7 8 9 1 2 3 456789 a0 write 0/1 d7 d6 d5 d4 d3 d2 d1 d0 1 zda
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 166 zdi block w rite the block write operation is initiated in the same manner as the single-byte write opera - tion, b ut instead of terminating the write operation after the ? rst data byte is transferred, the zdi master can continue to transmit additional bytes of data to the zdi sla v e on the ez80f92 de vice. after the receipt of each byte of data the zdi re gister address increments by 1. if the zdi re gister address reaches the end of the write only zdi re gister address space ( 30h ), the address stops incrementing. figure 42 illustrates the timing for zdi block write operations. zdi read operations zdi single-byte read single-byte read operations are initiated in the same manner as single-byte write opera - tions, with the e xception that the r/ w bit of the zdi re gister address is set to 1. upon receipt of a sla v e address with the r/ w bit set to 1, the ez80f92 de vice s zdi block loads the selected data into the shifter at the be ginning of the ? rst c ycle follo wing the single-bit data separator . the most-signi? cant bit ( msb) is shifted out ? rst. figure 43 illustrates the timing for zdi single-byte read operations. figure 42. zdi block data w rite t iming zdi data bytes lsb of zdi address single-bit byte separator msb of data byte 2 msb of data byte 1 lsb of data byte 1 single-bit byte separator zcl 7 8 9 1 2 3 789129 a0 write 0/1 d7 d6 d5 d1 d0 0/1 d7 d6 1 zda
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 167 zdi block read a block read operation is initiated the same as a single-byte read; ho we v er , the zdi master continues to clock in the ne xt byte from the zdi sla v e as the zdi sla v e continues to output data. the zdi re gister address counter increments with each read. if the zdi re gis - ter address reaches the end of the read only zdi re gister address space ( 20h ), the address stops incrementing. figure 44 illustrates the zdi s block read timing. operation of the ez80f92 device during zdi breakpoints if the zdi forces the cpu to break, only the cpu suspends operation. the system clock continues to operate and dri v e other peripherals. those peripherals that can operate autonomously from the cpu may continue to operate, if so enabled. f or e xample, the w atch-dog t imer and programmable reload t imers continue to count during a zdi break point. figure 43. zdi single-byte data read t iming figure 44. zdi block data read t iming zdi data byte lsb of zdi address single-bit byte separator lsb of data msb of data end of data or new zdi start signal zcl 7 8 9 1 2 3 456789 a0 read 0/1 d7 d6 d5 d4 d3 d2 d1 d0 1 zda zdi data bytes lsb of zdi address single-bit byte separator msb of data byte 2 msb of data byte 1 lsb of data byte 1 single-bit byte separator zcl 7 8 9 1 2 3 789129 a0 read 0/1 d7 d6 d5 d1 d0 0/1 d7 d6 1 zda
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 168 when using the zdi interf ace, an y write or read operations of peripheral re gisters in the i/o address space produces the same ef fect as read or write operations using the cpu. because man y re gister read/write operations e xhibit secondary ef fects, such as clearing ? ags or causing operations to commence, the ef fects of the read/write operations during a zdi break must be tak en into consideration. bus requests during zdi debug mode the zdi block on the ez80f92 de vice allo ws an e xternal de vice to tak e control of the address and data b us while the ez80f92 de vice is in debug mode. zdi_b usa ck_en causes zdi to allo w or pre v ent ackno wledgement of b us requests by e xternal peripherals. the b us ackno wledge only occurs at the end of the current zdi operation (indicated by a high during the single-bit byte separator). the def ault reset condition is for b us ackno wl - edgement to be disabled. t o allo w b us ackno wledgement, the zdi_b usa ck_en must be written. when an e xternal b us request ( b usreq pin asserted) is detected, zdi w aits until comple - tion of the current operation before responding. zdi ackno wledges the b us request by asserting the b us ackno wledge ( b usa ck ) signal. if the zdi block is not currently shift - ing data, it ackno wledges the b us request immediately . zdi uses the single-bit byte separa - tor of each data w ord to determine if it is at the end of a zdi operation. if the bit is a logical 0, zdi does not assert b usa ck to allo w additional data read or write operations. if the bit is a logical 1, indicating completion of the zdi commands, b usa ck is asserted. potential hazards of enabling bus requests during debug mode there are some potential hazards that the user must be a w are of when enabling e xternal b us requests during zdi debug mode. first, when the address and data b us are being used by an e xternal source, zdi must only access zdi re gisters and internal cpu re gisters to pre v ent possible bus contention. the b us ackno wledge status is reported in the zdi_b us_st a t re gister . the b usa ck output pin also indicates the b us ackno wledge state. a second hazard is that when a b us ackno wledge is granted, the zdi is subject to an y w ait states that are assigned to the de vice currently being accessed by the e xternal peripheral. t o pre v ent data errors, zdi should a v oid data transmission while another de vice is controlling the b us. finally , e xiting zdi debug mode while an e xternal peripheral controls the address and data b uses, as indicated by b usa ck assertion, may produce unpredictable results.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 169 zdi write only registers t able 95 lists the zdi write only re gisters. man y of the zdi write only addresses are shared with zdi read only re gisters. t able 95. zdi w rite only registers zdi address zdi register name zdi register function reset v alue 00h zdi_addr0_l address match 0 low byte xxh 01h zdi_addr0_h address match 0 high byte xxh 02h zdi_addr0_u address match 0 upper byte xxh 04h zdi_addr1_l address match 1 low byte xxh 05h zdi_addr1_h address match 1 high byte xxh 06h zdi_addr1_u address match 1 upper byte xxh 08h zdi_addr2_l address match 2 low byte xxh 09h zdi_addr2_h address match 2 high byte xxh 0ah zdi_addr2_u address match 2 upper byte xxh 0ch zdi_addr3_l address match 3 low byte xxh 0dh zdi_addr3_h address match 3 high byte xxh 0eh zdi_addr3_u address match 4 upper byte xxh 10h zdi_brk_ctl break control register 00h 11h zdi_master_ctl master control register 00h 13h zdi_wr_data_l write data low byte xxh 14h zdi_wr_data_h write data high byte xxh 15h zdi_wr_data_u write data upper byte xxh 16h zdi_rw_ctl read/write control register 00h 17h zdi_bus_ctl bus control register 00h 21h zdi_is4 instruction store 4 xxh 22h zdi_is3 instruction store 3 xxh 23h zdi_is2 instruction store 2 xxh 24h zdi_is1 instruction store 1 xxh 25h zdi_is0 instruction store 0 xxh 30h zdi_wr_mem write memory register xxh
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 170 zdi read only registers t able 96 lists the zdi read only re gisters. man y of the zdi read only addresses are shared with zdi write only re gisters. zdi register definitions zdi address match registers the four sets of address match re gisters are used for setting the addresses for generating break points. when the accompan ying brk_addrx bit is set in the zdi break control re gister to enable the particular address match, the current ez80f92 address is compared with the 3-byte address set, {zdi_addrx_u, zdi_addrx_h, zdi_addr_x_l}. if the cpu is operating in adl mode, the address is supplied by addr[23:0]. if the cpu is operating in z80 mode, the address is supplied by {mb ase[7:0], addr[15:0]}. if a match is found, zdi issues a break to the ez80f92 de vice placing the processor in zdi mode pending further instructions from the zdi inter - f ace block. if the address is not the ? rst op-code fetch, the zdi break is e x ecuted at the end of the instruction in which it is e x ecuted. there are four sets of address match re gis - ters. the y can be used in conjunction with each other to break on branching instruc - tions. see t able 97 . t able 96. zdi read only registers zdi address zdi register name zdi register function reset v alue 00h zdi_id_l ez80 product id low byte register 07h 01h zdi_id_h ez80 product id high byte register 00h 02h zdi_id_rev ez80 product id revision register xxh 03h zdi_stat status register 00h 10h zdi_rd_l read memory address low byte register xxh 11h zdi_rd_h read memory address high byte register xxh 12h zdi_rd_u read memory address upper byte register xxh 17h zdi_bus_stat bus status register 00h 20h zdi_rd_mem read memory data value xxh
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 171 zdi break control register the zdi break control re gister is used to enable break points. zdi asserts a break when the cpu instruction address, addr[23:0], matches the value in the zdi address match 3 registers, {zdi_addr3_u, zdi_addr3_h, zdi_addr3_l}. breaks can only occur on an instruction boundary. if the instruction address is not the beginning of an instruction (that is, for multibyte instructions), then the break occurs at the end of the current instruction. the brk_next bit is set to 1. the brk_next bit must be reset to 0 to release the break. see t able 98 . t able 97. zdi address match register s (z di_addr0_l = 00h, zdi_addr0_h = 01h, zdi_addr0_u = 02h , z di_addr1_l = 04h, zdi_addr1_h = 05h, z di_addr1_u = 06h , z di_addr2_l = 08h, zdi_addr2_h = 09h, z di_addr2_u = 0ah , z di_addr3_l = 0ch, zdi_addr3_h = 0dh, and zdi_addr3_u = 0eh in the zdi register w rite only address space ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: w = write only. bit position v alue description [7:0] zdi_addr x _l, zdi_addr x _h, or zdi_addr x _u 00hC ffh the four sets of zdi address match registers are used for setting the addresses for generating break points. the 24-bit addresses are supplied by {zdi_addrx_u, zdi_addrx_h, zdi_addrx_l, where x is 0, 1, 2, or 3.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 172 t able 98. zdi break control registe r (z di_brk_ctl = 10h in the zdi w rite only register address space ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write only. bit position v alue description 7 brk_next 0 the zdi break on the ne xt cpu instruction is disabled. clearing this bit releases the cpu from its current break condition. 1 the zdi break on th e next cpu instruction is enabled. the cpu can use multibyte op codes and multibyte operands. break points only occur on the first op code in a multibyte op code instruction. if the zcl pin is high and the zda pin is low at the end of reset, this bit is set to 1 and a break occurs on the first instruction following the reset. this bit is set automatically during zdi break on address match. a break can also be forced by writing a 1 to this bit. 6 brk_addr3 0 the zdi break, upon matching break address 3, is disabled. 1 the zdi break, upon matching break address 3, is enabled. 5 brk_addr2 0 the zdi break, upon matching break address 2, is disabled. 1 the zdi break, upon matching break address 2, is enabled. 4 brk_addr1 0 the zdi break, upon matching break address 1, is disabled. 1 the zdi break, upon matching break address 1, is enabled. 3 brk_addr0 0 the zdi break, upon matching break address 0, is disabled. 1 the zdi break, upon matching break address 0, is enabled.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 173 2 ign_low_1 0 the ignore the low byte function of the zdi address match 1 registers is disabled. if brk_addr1 is set to 1, zdi initiates a break when the entire 24-bit address, addr[23:0], matches the 3-byte value {zdi_addr1_u, zdi_addr1_h, zdi_addr1_l}. 1 the ignore the low byte function of the zdi address match 1 registers is enabled. if brk_addr1 is set to 1, zdi initiates a break when only the upper 2 bytes of the 24-bit address, addr[23:8], match the 2-byte value {zdi_addr1_u, zdi_addr1_h}. as a result, a break can occur anywhere within a 256-byte page. 1 ign_low_0 0 the ignore the low byte function of the zdi address match 1 registers is disabled. if brk_addr0 is set to 1, zdi initiates a break when the entire 24-bit address, addr[23:0], matches the 3-byte value {zdi_addr0_u, zdi_addr0_h, zdi_addr0_l}. 1 the ignore the low byte function of the zdi address match 1 registers is enabled. if the brk_addr1 is set to 0, zdi initiates a break when only the upper 2 bytes of the 24-bit address, addr[23:8], match the 2 bytes value {zdi_addr0_u, zdi_addr0_h}. as a result, a break can occur anywhere within a 256-byte page. 0 single_step 0 zdi single step mode is disabled. 1 zdi single step mode is enabled. zdi asserts a break following execution of each instruction. bit position v alue description
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 174 zdi master control register the zdi master control re gister pro vides control of the ez80f92 de vice. it is capable of forcing a reset and w aking up the ez80f92 de vice from the lo w-po wer modes ( hal t or sleep). see t able 99 . t able 99. zdi master control registe r (z di_master_ctl = 1 1h in zdi register w rite address spaces ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write only. bit position v alue description 7 zdi_reset 0 no action. 1 initiate a reset of the cpu . this bit is automatically cleared at the end of the reset event. [6:0] 0000000 reserved.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 175 zdi w rite data registers these three re gisters are used in the zdi write only re gister address space to store the data that is written when a write instruction is sent to the zdi read/write control re gister (zdi_r w_ctl). the zdi read/write control re gister is located at zdi address 16h immediately follo wing the zdi write data re gisters. as a result, the zdi master is allo wed to write the data to {zdi_wr_u, zdi_wr_h, zdi_wr_l} and the write com - mand in one data transfer operation. see t able 100 . zdi read/w rite control register the zdi read/write control re gister is used in the zdi write only re gister address to read data from, write data to, and manipulate the cpu s re gisters or memory locations. when this re gister is written, the ez80f92 de vice immediately performs the operation cor - responding to the data v alue written as described in t able 101 . when a read operation is e x ecuted via this re gister , the requested data v alues are placed in the zdi read data re gis - ters {zdi_rd_u, zdi_rd_h, zdi_rd_l}. when a write operation is e x ecuted via this re gister , the write data is tak en from the zdi write data re gisters {zdi_wr_u, zdi_wr_h, zdi_wr_l}. see t able 101 . refer to the ez80 cpu user manual (um0077) for information re g arding the cpu re gisters. t able 100. zdi w rite data register s (z di_wr_u = 13h, zdi_wr_h = 14h, and zdi_wr_l = 15h in the zdi register w rite only address space ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: x = undefined; w = write. bit position v alue description [7:0] zdi_wr_l, zdi_wr_h, or zdi_wr_l 00hC ffh these registers contain the data that is written during execution of a write operation defined by the zdi_rw_ctl register. the 24-bit data value is stored as {zdi_wr_u, zdi_wr_h, zdi_wr_l}. if less than 24 bits of data are required to complete the required operation, the data is taken from the least-significant byte(s).
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 176 t able 101. zdi read/w rite control register function s (z di_r w_ctl = 16h in the zdi register w rite only address space ) hex v alue command hex v alue command 00 read {mbase, a, f} zdi_rd_u mbase zdi_rd_h f zdi_rd_l a 80 write af mbase zdi_wr_u f zdi_wr_h a zdi_wr_l 01 read bc zdi_rd_u bcu zdi_rd_h b zdi_rd_l c 81 write bc bcu zdi_wr_u b zdi_wr_h c zdi_wr_l 02 read de zdi_rd_u deu zdi_rd_h d zdi_rd_l e 82 write de deu zdi_wr_u d zdi_wr_h e zdi_wr_l 03 read hl zdi_rd_u hlu zdi_rd_h h zdi_rd_l l 83 write hl hlu zdi_wr_u h zdi_wr_h l zdi_wr_l 04 read ix zdi_rd_u ixu zdi_rd_h ixh zdi_rd_l ixl 84 write ix ixu zdi_wr_u ixh zdi_wr_h ixl zdi_wr_l 05 read iy zdi_rd_u iyu zdi_rd_h iyh zdi_rd_l iyl 85 write iy iyu zdi_wr_u iyh zdi_wr_h iyl zdi_wr_l 06 read sp in adl mode, sp = spl. in z80 mode, sp = sps. 86 write sp in adl mode, sp = spl. in z80 mode, sp = sps. 07 read pc zdi_rd_u pc[23:16] zdi_rd_h pc[15:8] zdi_rd_l pc[7:0] 87 write pc pc[23:16] zdi_wr_u pc[15:8] zdi_wr_h pc[7:0] zdi_wr_l 08 set adl adl 1 88 reserved the ez80 ? cpus alternate register set (a, f, b, c, d, e, hl) cannot be read directly. the zdi programmer must execute the exchange instruction (exx) to gain access to the alternate ez80 ? cpu register set.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 177 09 reset adl adl 0 89 reserved 0a exchange cpu register sets af af bc bc de de hl hl 8a reserved 0b read memory from current pc value, increment pc 8b write memory from current pc value, increment pc t able 101. zdi read/w rite control register function s (z di_r w_ctl = 16h in the zdi register w rite only address space (continued) ) hex v alue command hex v alue command the ez80 ? cpus alternate register set (a, f, b, c, d, e, hl) cannot be read directly. the zdi programmer must execute the exchange instruction (exx) to gain access to the alternate ez80 ? cpu register set.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 178 zdi bus control register the zdi bus control re gister controls b us requests during debug mode. it enables or disables b us ackno wledge in zdi debug mode and allo ws zdi to force assertion of the b usa ck signal. this re gister should only be written during zdi debug mode (that is, follo wing a break). see t able 102 . t able 102. zdi bus control registe r (z di_bus_ctl = 17h in the zdi register w rite only address space ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write only. bit position v alue description 7 zdi_busak_en 0 bus requests by external peripherals using the busreq pin are ignored. the bus acknowledge signal, busack , is not asserted in response to any bus requests. 1 bus requests by external peripherals using the busreq pin are accepted. a bus acknowledge occurs at the end of the current zdi operation. the bus acknowledge is indicated by asserting the busack pin in response to a bus request. 6 zdi_busak 0 deassert the bus acknowledge pin ( busack ) to return control of the address and data buses back to zdi. 1 assert the bus acknowledge pin ( busack ) to pass control of the address and data buses to an external peripheral. [5:0] 000000 reserved.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 179 instruction store 4:0 registers the zdi instruction store re gisters are located in the zdi re gister write only address space. the y can be written with instruction data for direct e x ecution by the cpu. when the zdi_is0 re gister is written, the ez80f92 de vice e xits the zdi break state and e x e - cutes a single instruction. the op codes and operands for the instruction come from these instruction store re gisters. the instruction store re gister 0 is the ? rst byte fetched, fol - lo wed by instruction store re gisters 1, 2, 3, and 4, as necessary . only the bytes the proces - sor requires to e x ecute the instruction must be stored in these re gisters. some cpu instructions, when combined with the memory mode suf ? x es (.sis, .sil, .lis, or .lil), require 6 bytes to operate. these 6-byte instructions cannot be e x ecuted directly using the zdi instruction store re gisters. see t able 103 . the instruction store 0 re gister is located at a higher zdi address than the other instruction store re gisters. this feature allo ws the use of the zdi auto-address increment function to load and e x ecute a multibyte instruction with a single data stream from the zdi master . ex ecution of the instruction commences with writing the most recent byte to zdi_is0. t able 103. instruction store 4:0 register s (z di_is4 = 21h, zdi_is3 = 22h, zdi_is2 = 23h, zdi_is1 = 24h , a nd zdi_is0 = 25h in the zdi register w rite only address space ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: x = undefined; w = write. bit position v alue description [7:0] zdi_is4, zdi_is3, zdi_is2, zdi_is1, or zdi_is0 00hC ffh these registers contain the op codes and operands for immediate execution by the cpu following a write to zdi_is0. the zdi_is0 register contains the first op code of the instruction. the remaining zdi_isx registers contain any additional op codes or operand dates required for execution of the required instruction. note:
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 180 zdi w rite memory register a write to the zdi write memory re gister causes the ez80f92 de vice to write the 8-bit data to the memory location speci? ed by the current address in the program counter . in z80 memory mode, this address is {mb ase, pc[15:0]}. in adl memory mode, this address is pc[23:0]. the program counter , pc, increments after each data write. ho we v er , the zdi re gister address does not increment automatically when this re gister is accessed. as a result, the zdi master is allo wed to write an y number of data bytes by writ - ing to this address one time follo wed by an y number of data bytes. see t able 104 . t able 104. zdi w rite memory registe r (z di_wr_mem = 30h in the zdi register w rite only address space ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access w w w w w w w w note: x = undefined; w = write. bit position v alue description [7:0] zdi_wr_mem 00hC ffh the 8-bit data that is transferred to the zdi slave following a write to this address is written to the address indicated by the current program counter. the program counter is incremented following each 8 bits of data. in z80 memory mode, ({mbase, pc[15:0]}) 8 bits of transferred data. in adl memory mode, (pc[23:0]) 8-bits of transferred data.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 181 ez80 product id low and high byte registers the ez80 product id lo w and high byte re gisters combine to pro vide a means for an e xternal de vice to determine the particular ez80acclaim! ? product being addressed. see t ables 105 and 106 . t able 105. ez80 product id low byte registe r (z di_id_l = 00h in the zdi register read only address space ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 1 1 1 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] zdi_id_l 07h {zdi_id_h, zdi_id_l} = {00h, 07h} indicates the ez80f92 product. t able 106. ez80 product id high byte registe r (z di_id_h = 01h in the zdi register read only address space ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] zdi_id_h 00h {zdi_id_h, zdi_id_l} = {00h, 07h} indicates the ez80f92 product.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 182 ez80 product id revision register the ez80 product id re vision re gister identi? es the current re vision of the ez80f92 prod - uct. see t able 107 . zdi status register the zdi status re gister pro vides current information about t he ez80f92 de vice. see t able 108 . t able 107. ez80 product id revision registe r (z di_id_rev = 02h in the zdi register read only address space ) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r r r r r r r r note: x = undetermined; r = read only. bit position v alue description [7:0] zdi_id_rev 00hC ffh identifies the current revision of the ez80f92 product. t able 108. zdi status registe r (z di_st a t = 03h in the zdi register read only address space ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description 7 zdi_active 0 the cpu is not functioning in zdi mode. 1 the cpu is currently functioning in zdi mode. 6 0 reserved. 5 halt_slp 0 the cpu is not currently in halt or sleep mode. 1 the cpu is currently in halt or sleep mode.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 183 zdi read register low , high, and upper the zdi re gister read only address space of fers lo w , high, and upper functions, which contain the v alue read by a read operation from the zdi read/write control re gister (zdi_r w_ctl). this data is v alid only while in zdi break mode and only if the instruction is read by a request from the zdi read/write control re gister . see t able 109 . 4 adl 0 the cpu is operating in z80 memory mode. (adl bit = 0) 1 the cpu is operating in adl memory mode. (adl bit = 1) 3 madl 0 the cpus mixed-memory mode (madl) bit is reset to 0. 1 the cpus mixed-memory mode (madl) bit is set to 1. 2 ief1 0 the cpus interrupt enable flag 1 is reset to 0. maskable interrupts are disabled. 1 the cpus interrupt enable flag 1 is set to 1. maskable interrupts are enabled. [1:0] 00 reserved. t able 109. zdi read register low , high and uppe r (z di_rd_l = 10h, zdi_rd_h = 1 1h, and zdi_rd_u = 12h in the zdi register read only address space ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] zdi_rd_l, zdi_rd_h, or zdi_rd_u 00hC ffh values read from the memory location as requested by the zdi read control register during a zdi read operation. the 24-bit value is supplied by {zdi_rd_u, zdi_rd_h, zdi_rd_l}. bit position v alue description
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 184 zdi bus status register the zdi bus status re gister monitors b usa cks during zdi debug mode. see t able 110 . zdi read memory register when a read is e x ecuted from the zdi read memory re gister , the ez80f92 de vice fetches the data from the memory address currently pointed to by the program counter , pc; the program counter is then incremented. in z80 memory mode, the memory address is {mb ase, pc[15:0]}. in adl memory mode, the memory address is pc[23:0]. refer to the ez80 cpu user manual (um0077) for more information re g arding z80 and adl memor y modes. the program counter , pc, increments after each data read. ho we v er , the zdi re gister address does not increment automatically when this re gister is accessed. as a result, the zdi master can read an y number of data bytes out of memory through the zdi read memory re gister . see t able 111 . t able 1 10. zdi bus control registe r (z di_bus_st a t = 17h in the zdi register read only address space ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description 7 zdi_busack_en 0 bus requests by external peripherals using the busreq pin are ignored. the bus acknowledge signal, busack , is not asserted. 1 bus requests by external peripherals using the busreq pin are accepted. a bus acknowledge occurs at the end of the current zdi operation. the bus acknowledge is indicated by asserting the busack pin. 6 zdi_bus_stat 0 address and data buses are not relinquished to an external peripheral. bus acknowledge is deasserted ( busack pin is high). 1 address and data buses are relinquished to an external peripheral. bus acknowledge is asserted ( busack pin is low). [5:0] 000000 reserved.
ps015309-1004 preliminary zilog debug interface ez80f92/ez80f93 product specification 185 t able 1 1 1. zdi read memory registe r (z di_rd_mem = 20h in the zdi register read only address space ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r r r note: r = read only. bit position v alue description [7:0] zdi_rd_mem 00hC ffh 8-bit data read from the memory address indicated by the cpus program counter. in z80 memory mode, 8-bit data is transferred out from address {mbase, pc[15:0]}. in adl memory mode, 8-bit data is transferred out from address pc[23:0].
ps015309-1004 preliminary on-chip instrumentation ez80f92/ez80f93 product specification 186 on-chip instrumentation introduction to on-chip instrumentation on-chip instrumentation 1 (oci?) for the ez80 ? cpu core enables po werful deb ugging features. the oci pro vides run control, memory and re gister visibility , comple x break - points, and trace history features. the oci emplo ys all of the functions of the zilog deb ug interf ace ( zdi) as described in the zilog deb ug interf ace s ection that starts on page 161 . it also adds the follo wing deb ug features: ? control via a 4-pin joint t est action group ( jt a g )-standard p ort that conforms to the ieee standard 1149.1 ( t est access port and boundary scan architecture) 2 ? comple x break point trigger functions ? break point enhancements, such as the ability to: C de? ne tw o break point addresses that form a range C break on mask ed data v alues C start or stop trace C assert a trigger output signal ? t race history b uf fer ? softw are break point instruction there are four sections to the oci: ? jt a g interf ace ? zdi deb ug control ? t race b uf fer memory ? comple x triggers oci activation oci features clock initialization circuitry so that e xternal deb ug hardw are can be detected during po wer -up. the e xternal deb ugger must dri v e the oci clock pin ( tck) lo w at least tw o system clock c ycles prior to the end of the reset to acti v ate the oci block. if tck is high at the end of the reset , the oci block shuts do wn so that it does not dra w po wer in normal product operation. when the oci is shut do wn, zdi is enabled directly and can 1. on-chip instrumentation and oci are trademarks of first silicon solutions, inc. 2. the ez80f92 does not contain the boundary scan register required for 1149.1 compliance.
ps015309-1004 preliminary on-chip instrumentation ez80f92/ez80f93 product specification 187 be accessed via the clock (tck) and data ( tdi) pins. see the zilog deb ug interf ace sec - tion on page 161 for more information about z di. oci interface there are ? v e dedicated pins on the ez80f92 de vice for the oci interf ace. f our pins tck, tms, tdi, and tdoare required for ieee standard 1149.1-compliant jt a g ports. the trigout pin pro vides additional testability features. these ? v e oci pins are described in t able 112 . t able 1 12. oci pins symbol name t ype description tck clock. input asynchronous to the primary cpu system clock. the tck period must be at least twice the system clock period. during reset, this pin is sampled to select either oci or zdi debug modes. if low during reset, the oci is enabled. if high during reset, the oci is powered down and zdi debug mode is enabled. when zdi debug mode is active, this pin is the zdi clock. on-chip pull-up ensures a default value of 1 (high). tms test mode select input this serial test mode input controls jtag mode selection. on-chip pull-up ensures a default value of 1 (high). the tms signal is sampled on the rising edge of the tck signal. tdi data in input (oci enabled) serial test data input. on-chip pull-up ensures a default value of 1 (high). this pin is input-only when the oci is enabled. the input data is sampled on the rising edge of the tck signal. i/o (oci disabled) when the oci is disabled, this pin functions as the zda (zdi data) i/o pin. tdo data out output the output data changes on the falling edge of the tck signal. trigout trigger output output generates an active high trigger pulse when valid oci trigger events occur. output is tristate when no data is being driven out.
ps015309-1004 preliminary on-chip instrumentation ez80f92/ez80f93 product specification 188 oci information requests f or additional information re g arding on-chip instrumentation, or to order oci deb ug tools, please contact: first silicon solutions, inc. 5440 sw w estgate drive, suite 240 portland, or 97221 phone: (503) 292-6730 fax: (503) 292-5840 www .fs2.com
ps015309-1004 preliminary random access memory ez80f92/ez80f93 product specification 189 random access memory the ez80f92 features 8 kb (8192 bytes) single-port data random access memory (ram) for general-purpose use. the ez80f93 features 4kb (4096 bytes) general-purpose ram. ram can be enabled or disabled, and it can be relocated to the top of an y 64 kb page in memory . data is passed to and from ram via the 8-bit data b us. on-chip ram operates with zero w ait states. f or the ez80f92, ram occupies memory addresses in the range {ram_addr_u[7:0], e000h } to {ram_addr_u[7:0], ffffh }. f ollo wing a reset , ram is enabled with ram_addr_u set to ffh . figure 45 illustrates a memory map of on-chip ram. in this e xample, the ram address upper byte re gister , ram_addr_u, is set to 7ah . figure 45 is not dra wn to scale, as ram occupies only a v ery small fraction of the a v ail - able 16 mb address space. f or the ez80f93 de vice, ram occupies memory addresses in the range {ram_addr_u[7:0], f000h } to {ram_addr_u[7:0], f000h }. f ollo wing a reset , ram is enabled with ram_addr_u set to ffh . figure 46 illustrates a memory map of on-chip ram. in this e xample, the ram address upper byte re gister , ram_addr_u, is set to 7ah . figure 45 is not dra wn to scale, as ram occupies only a v ery small fraction of the a v ailable 16 mb address space. figure 45. ez80f92 on-chip ram memory addressing example memory location ffffffh 7affffh 7ae000h 000000h ram_addr_u 7ah 8kb general purpose ram
ps015309-1004 preliminary random access memory ez80f92/ez80f93 product specification 190 when enabled, on-chip ram assumes priority o v er on-chip flash memory and an y mem - ory chip selects that can also be enabled in the same address space. if an address is gener - ated in a range that is co v ered by both the ram address space and a particular memory chip select address space, the memory chip select is not acti v ated. on-chip ram is not accessible by e xternal de vices during bus ackno wledge c ycles. figure 46. ez80f93 on-chip ram memory addressing example memory location ffffffh 7affffh 7af000h 000000h ram_addr_u 7ah 4kb general purpose ram
ps015309-1004 preliminary random access memory ez80f92/ez80f93 product specification 191 ram control registers ram control register the internal data ram can be disabled by clearing the ram_en bit. the def ault, upon reset , is for ram to be enabled. ram address upper byte register the ram_addr_u re gister de? nes the upper byte of the address for the on-chip ram. if enabled, ram addresses assume priority o v er all chip selects. the e xternal chip select signals are not asserted if the corresponding ram address is enabled. t able 1 13. ram control registe r (r am_ctl = 00b4h ) bit 7 6 5 4 3 2 1 0 reset 1 0 0 0 0 0 0 0 cpu access r/w r r r r r r r note: r/w = read/write; r = read only. bit position v alue description 7 ram_en 0 on-chip general-purpose ram is disabled. 1 on-chip general-purpose ram is enabled. [6:0] 0000000 reserved t able 1 14. ram address upper byte registe r (r am_addr_u = 00b5h ) bit 7 6 5 4 3 2 1 0 reset 1 1 1 1 1 1 1 1 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] ram_addr_u 00hC ffh this byte defines the upper byte of the ram address. on-chip ram is prioritized over all memory chip selects. if the enabled ram and chip select addresses overlap, the external chip select is not asserted.
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 192 flash memory flash memory arrangement in the ez80f92 the ez80f92 de vice features 128 kb (131,072 bytes) of non v olati v e flash memory with read/write/erase capability . the main flash memory array is arranged in 128 pages with 8 ro ws per page and 128 bytes per ro w . in addition to main flash memory , there are tw o separately-addressable ro ws which comprise a 256-byte information p age. the 128 kb of main storage can be protected in eight 16kb blocks. protecting a 16 kb block pre v ents write or erase operations. the flash memory arrangement is illustrated in figure 47 . figure 47. ez80f92 flash memory arrangement 8 32 kb blocks 16 2 kb pages per block 8 256-byte rows per page 256 single-byte columns per row 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 f d b 9 7 5 3 1 e c a 8 6 4 2 0 255 254 1 0
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 193 flash memory arrangement in the ez80f93 the ez80f92 features 64 kb (65,536 bytes) of non v olati v e flash memory with read/ write/erase capability . the main flash memory array is arranged in 64 pages with 8 ro ws per page and 128 bytes per ro w . in addition to the main flash memory there are tw o sepa - rately addressable ro ws which comprise a 256 byte information p age. the 64 kb of main storage can be protected in four 16 kb blocks. protecting a 16 kb block pre v ents write or erase operations. the flash memory arrangement is illustrated in figure 48 . flash memory overview flash can be programmed a single byte at a time or in b ursts of up to 128 bytes (full ro w). write operations may be accomplished using either memory or i/o instructions. reading flash memory can be accomplished via internal memory access or through the zdi and oci interf aces. the flash memory controller contains a frequenc y di vider , flash re gister interf ace, address generator , and the flash control state machine. a simpli? ed block dia - gram of the flash controller is illustrated in figure 49 . figure 48. ez80f93 flash memory arrangement 4 16-kb blocks 16 1-kb pages per block 8 128-byte rows per page 128 single-byte columns per row 3 2 1 0 7 6 5 4 3 2 1 0 f d b 9 7 5 3 1 e c a 8 6 4 2 0 127 126 1 0
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 194 programming flash memory flash memory is programmed using standard i/o or memory write operations which the flash memory controller automatically translates to the detailed timing and protocol required for flash memory . the more ef ? cient multibyte (ro w) programming mode is only a v ailable via i/o writes. t o ensure data inte grity and de vice reliability , tw o main restrictions e xist when programming flash memory: 1. the cumulati v e programming time subsequent to the most recent erase cannot e xceed 16 ms for an y gi v en ro w . 2. the same byte cannot be programmed more than twice subsequent to the most recent erase. single-byte i/o w rite operations a single-byte i/o write operation uses i/o re gisters for setting the column, page, and ro w address to be programmed. the flash_d a t a re gister stores the data to be written. while the cpu e x ecutes an output to i/o instruction to load the data into the flash_d a t a re gister , the flash controller asserts the internal w ait signal to stall the cpu until the flash write operation is complete. a single-byte write tak es between 66 s and 85 s to complete. programming an entire ro w (128 bytes) using single-byte writes therefore tak es at most 10.8 ms. this measure of time does not include the time required by the cpu to transfer data to the re gisters, which is a function of the instructions emplo yed and the system clock frequenc y . figure 49. flash memory block diagram flash_irq system clock ez80 core interface addr d cpud f addr out 17 8 17 8 8 8 9 out fd in fd out fcntl main_info clock divider 8-bit downcounter flash control registers flash state machine flash 256 kb + 512 bytes caution:
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 195 a typical sequence that performs a single-byte i/o write is detailed belo w . because the write is self-timed, the sequence can be repeated back-to-back without an y necessity for polling or interrupts. 1. write the flash_p a ge, flash_r o w , and flash_col re gisters with the address of the byte to be written. 2. write the data v alue to the flash_d a t a re gister . multibyte i/o w rite (row programming) multibyte i/o write operations use the same i/o re gisters as single-byte writes, b ut use an internal address incrementer for subsequent writes. multibyte writes allo w programming of a full ro w and are enabled by setting the r o w_pgm bit of the flash program control re gister . f or multibyte writes, the cpu sets the address re gisters, enables ro w program - ming, and then e x ecutes a output to i/o instruction with repeat to load the block of data into the flash_d a t a re gister . f or each indi vidual byte written to the flash_d a t a re gister during the block mo v e, the flash controller asserts the internal w ait signal to stall the cpu until the current byte has been programmed. during ro w programming, the flash controller continuously asserts flash s high v oltage until all bytes are programmed (column address < 127). as a consequence, the ro w can be programmed f aster than if the high v oltage is toggled for each byte. the per -byte program - ming time during ro w programming is between 41 s and 52 s. as such, programming the 128 bytes of a ro w in this mode tak es at most 6.7 ms, lea ving 9.3 ms for the o v erhead of cpu instructions used to fetch the 128 bytes. a typical sequence that performs a multibyte i/o write is sho wn in the follo wing sequence. 1. check the flash_irq re gister to be sure an y pre vious ro w program has completed. 2. write the flash_p a ge, flash_r o w , and flash_col re gisters with the address of the ? rst byte to be written. 3. set the r o w_pgm bit in the flash_pgctl re gister to enable ro w programming mode. 4. write the ne xt data v alue to the flash_d a t a re gister . 5. if the end of the ro w has not been reached, return to step 4 . during ro w programming, softw are must monitor the ro w time-out error bit either by enabling this interrupt or through polling. if a ro w time-out occurs, the flash controller aborts the ro w programming operation and softw are must then assure that no further writes are performed to the ro w without it ? rst being erased. it is suggested that ro w pro - gramming only be used one time per ro w and not in combination with single-byte writes to the same ro w without ? rst erasing it. otherwise, the b urden is on softw are to ensure that
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 196 the 16ms maximum cumulati v e programming time between erasures is not e xceeded for a ro w . memory w rite a single-byte memory write operation uses the address b us and data b us of the ez80f92 de vice for programming a single data byte to flash. while the cpu e x ecutes a load instruction, the flash controller asserts the internal w ait signal to stall the cpu until the write is complete. a single-byte write tak es between 66s and 85s to complete. pro - gramming an entire ro w using memory writes therefore tak es at most 10.8ms. this time does not include time required by the cpu to transfer data to the re gisters which is a func - tion of the instructions emplo yed and the system clock frequenc y . the memory write function does not support multibyte ro w programming. because mem - ory writes are self-timed, the y can be performed back-to-back without an y necessity for polling or interrupts. erasing flash memory erasing bytes in flash memory returns them to a v alue of ffh. both the mass and p age erase operations are self-timed by the flash controller , lea ving the cpu free to e x ecute other operations in parallel. the done status bit in the flash interrupt control re gister can be polled by softw are or used as an interrupt source to signal completion of an erase operation. if the cpu attempts to access flash while an erase is in progress, the flash con - troller forces a w ait state until the erase operation completes. mass erase performing a mass erase operation on flash memory erases all bits in flash, including the information p age. this self-timed operation tak es approximately 200 ms to complete. page erase the smallest erasable unit in flash memory is a page. which of the main flash memory pages or the single information p age is to be erased is determined by the setting of the flash_p a ge re gister . this self-timed operation tak es approximately 10 ms to complete. flash control registers the flash re gister interf ace contains all the re gisters used in flash memory . the de? ni - tions belo w describe each re gister . flash key register writing the tw o-byte sequence b6h , 49h in immediate succession to this re gister unlocks the flash di vider and flash write/erase protection re gisters. if these v alues are not writ -
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 197 ten by consecuti v e cpu i/o writes (i/o reads and memory read/writes produce no ef fect), the flash di vider and flash write/erase protection re gisters remain lock ed to pre - v ent accidental o v erwrites of these critical flash control re gister settings. writing a v alue to either the flash frequenc y di vider re gister or the flash write/erase protection re gister automatically relocks both of the re gisters ag ain. flash data register the flash data re gister stores the data v alues to be programmed to flash memory via i/o write operations. this re gister is used for all i/o write access to flash, both indi vidual byte writes and multibyte ro w programming. f or single-byte i/o write operations, a single-byte write to this i/o re gister programs the data v alue into the single-byte location pointed to by the page, ro w , and column re gisters. f or multibyte i/o write operations, the flash controller autoincrements the column address for each byte placed into this re gister . a maximum of 128 bytes of data can be pro - grammed into flash during a multibyte i/o write operation. the r o w_pgm bit in the flash program control re gister must be set to 1 prior to be ginning a multibyte i/o write operation. this re gister does not return data from flash memory . if read, this re gister returns the most recent data v alue written to the re gister . t able 1 15. flash key registe r (f lash_key = 00f5h ) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access w w w w w w w w note: w = write only. bit position v alue description [7:0] flash_key b6h, 49h sequential write operations of the values {b6h, 49h} to this register unlock the flash frequency divider and flash write/ erase protection registers.
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 198 flash address upper byte register the flash_addr_u re gister de? nes the upper 7 bits of the address for flash memory . changing the v alue of flash_addr_u allo ws the on-chip 128 kb/64 kb flash mem - ory to be mapped to an y location within the 16 mb linear address space of the ez80f92 de vice. if the on-chip flash memory is enabled, flash address assumes priority o v er an y e xternal chip selects. the e xternal chip select signals are not asserted if the correspond - ing flash address is enabled. the internal flash memory does not hold priority o v er inter - nal sram. t able 1 16. flash data registe r ( flash_da t a = 00f6h) bit 7 6 5 4 3 2 1 0 reset x x x x x x x x cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write. bit position v alue description [7:0] flash_data 00hC ffh data value to be written to flash during an i/o write operation. t able 1 17. flash address upper byte registe r ( flash_addr_u = 00f7h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r note: r/w = read/write; r = read only. bit position v alue description [7:1] flash_addr_u 00hC feh these bits define the upper byte of the flash address. when on-chip flash is enabled, the flash address space begins at address {flash_addr_u, 0b, 0000h}. on-chip flash is prioritized over all external chip selects. 0 0 reserved (enforces alignment on a 128 kb boundary).
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 199 flash control register the flash control re gister enables or disables memory access to flash. i/o access to the flash control re gisters and i/o programming to flash memory are still possible while flash memory space access is disabled. the minimum access time of the internal flash is 60 ns. the flash control re gister must be con? gured to pro vide the appropriate number of w ait states based on the system clock frequenc y of the ez80f92 de vice. def ault on reset is for 4 w ait states to be inserted for flash memory access. t able 1 18. flash control register (flash_ctrl= 00f8h) bit 7 6 5 4 3 2 1 0 reset 1 0 0 0 1 0 0 0 cpu access r/w r/w r/w r r/w r r r note: r/w = read/write, r = read only. bit position v alue description [7:5] flash_wait 000 0 wait states are inserted when flash is active. 001 1 wait state is inserted when flash is active. 010 2 wait states are inserted when flash is active. 011 3 wait states are inserted when flash is active. 100 4 wait states are inserted when flash is active. 101 5 wait states are inserted when flash is active. 110 6 wait states are inserted when flash is active. 111 7 wait states are inserted when flash is active. [4] 0 reserved [3] flash_en 0 flash memory access is disabled. 1 flash memory access is enabled. [2:0] 000 reserved
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 200 flash frequency divider register the 8-bit frequenc y di vider allo ws programming to flash o v er a range of system clock fre - quencies. flash can programmed with system clock frequencies ranging from 154 khz through 50 mhz. the flash controller requires an input clock with a period that f alls within the range of 5.1 ? 6.5 s. the period of the flash controller clock is set via the flash frequenc y di vider re gister . writes to this re gister are allo wed only after it is unlock ed via the flash_key re gister . the frequenc y di vider re gister v alue required vs. system clock frequenc y is detailed in t able 119 . system clock frequencies outside of the ranges sho wn in this table are not supported. t able 1 19. flash frequency divider v alues system clock frequency flash frequency divider v alue 154C196 khz 1 308C392 khz 2 462C588 khz 3 616 khzC50 mhz ceiling[system clock frequency (mhz) x 5.1 ( s)]* note: * the ceiling function rounds fractional values up to the next whole number, e.g., ceiling(3.01) is 4. t able 120. flash frequency divider register (flash_fdiv = 00f9h) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 1 cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w note: r/w = read/write, r = read only. *key sequence required to enable writes bit position v alue description [7:0] flash_fdiv 01hC ffh divider value for generating the required 5.1C6.5 s flash controller clock period.
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 201 flash w rite/erase protection register the flash write/erase protection re gister pre v ents accidental write or erase operations. the protection is limited to a resolution of eight 16 kb blocks. setting a bit to 1 protects that 16 kb block of flash memory from accidental writing or erasure. def ault on reset is for all flash memory blocks to be protected. a protect bit is not a v ailable for the information p age. mass erase is pre v ented if an y of the bits in this re gister are set to 1. writes to this re gister are allo wed only after it is unlock ed via the flash_key re gister . an y attempted writes to this re gister while lock ed sets it to ffh , thereby protecting all blocks. t able 121. flash w rite/erase protection registe r ( flash_prot= 00f ah) bit 7 6 5 4 3 2 1 0 reset 1 1 1 1 1 1 1 1 cpu access r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* note: r/w = read/write if unlocked, r = read only if locked. *key sequence required to unlock. bit position v alue description [7]* blk7_prot 0 disable write/erase protect on block 0x1c000 to 0x1ffff 1 enable write/erase protect on block 0x1c000 to 0x1ffff [6]* blk6_prot 0 disable write/erase protect on block 0x18000 to 0x1bfff 1 enable write/erase protect on block 0x18000 to 0x1bfff [5]* blk5_prot 0 disable write/erase protect on block 0x14000 to 0x17fff 1 enable write/erase protect on block 0x14000 to 0x17fff [4]* blk4_prot 0 disable write/erase protect on block 0x10000 to 0x13fff 1 enable write/erase protect on block 0x10000 to 0x13fff [3] blk3_prot 0 disable write/erase protect on block 0x0c000 to 0x0ffff 1 enable write/erase protect on block 0x0c000 to 0x0ffff [2] blk2_prot 0 disable write/erase protect on block 0x08000 to 0x0bfff 1 enable write/erase protect on block 0x08000 to 0x0bfff [1] blk1_prot 0 disable write/erase protect on block 0x04000 to 0x07fff 1 enable write/erase protect on block 0x04000 to 0x07fff note: *unused in the ez80f93 device. note:
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 202 flash interrupt control register there are tw o sources of interrupts from the flash controller . these tw o sources are: ? p age erase, mass erase, or ro w program completed successfully ? an error condition occurred either or both of the tw o interrupt sources can be enabled by setting the appropriate bits in the flash interrupt control re gister . the flash interrupt control re gister contains four status bits to indicate the follo wing error conditions: ? ro w pr ogram t ime-out . this bit signals a time-out during ro w programming. if the current ro w program operation does not complete within 2,432 flash controller clocks (12.4C15.8 ms depending on the flash controller clock period), the flash con - troller terminates the ro w program operation by clearing bit 2 of the flash program control re gister and setting the rp_tmo error bit to 1. ? write v iolation . this bit indicates an attempt to write to a protected block of flash memory (the write is not performed). ? p age erase v iolation . this bit indicates an attempt to erase a protected block of flash memory (the requested page is not erased). ? mass erase v iolation . this bit indicates an attempt to mass erase when there are one more protected blocks in flash memory (the mass erase is not performed). if the error condition interrupt is enabled, an y of the four error conditions result in an interrupt request being sent to the ez80f92 de vice s interrupt controller . reading the flash interrupt control re gister clears all error condition ? ags and the done ? ag. [0] blk0_prot 0 disable write/erase protect on block 0x00000 to 0x03fff 1 enable write/erase protect on block 0x00000 to 0x03fff bit position v alue description note: *unused in the ez80f93 device.
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 203 flash page select register the msb of this re gister is used to select whether all flash access and p age erases are directed to the 256-byte information p age or to the main flash memory array . when the main array is selected, the lo wer 7-bits (6 bits in the ez80f93 de vice) are used to select one of the 128 pages for p age erase or i/o write operations. t o perform a p age erase, the softw are must set the proper page v alue prior to setting the p age erase bit in the flash control re gister . t able 122. flash interrupt control registe r ( flash_irq= 00fbh) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r r r r r r note: r/w = read/write, r = read only. read resets bits [5] and [3:0]. bit position v alue description [7] done_ien 0 flash erase/row program done interrupt is disabled 1 flash erase/row program done interrupt is enabled [6] err_ien 0 error condition interrupt is disabled 1 error condition interrupt is enabled [5] done 0 erase/row program done flag is not set 1 erase/row program done flag is set [4] 0 reserved [3] wr_vio 0 the write violation error flag is not set. 1 the write violation error flag is set. [2] rp_tmo 0 the row program time-out error flag is not set. 1 the row program time-out error flag is set. [1] pg_vio 0 the page erase violation error flag is not set. 1 the page erase violation error flag is set. [0] mass_vio 0 the mass erase violation error flag is not set. 1 the mass erase violation error flag is set.
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 204 flash row select register the flash ro w select re gister is a 3-bit v alue used to de? ne one of the 8 ro ws of flash memory on a single page. this re gister is used for all i/o write access to flash. t able 123. flash page select registe r ( flash_p age= 00fch) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r/w r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write, r = read only. bit position v alue description [7] info_en 0 flash accesses main flash memory. 1 flash accesses the information page. page erase and mass erase operations affect the information page only. [6:0]* flash_page 00hC 7fh page address of flash memory to be used during the page erase or i/o write of the main flash memory. when info_en is set to 1, this field is ignored. note: *only 6 bits are available in the ez80f93 device. t able 124. flash row select registe r ( flash_row= 00fdh) bit 7 6 5 4 3 2 1 0 reset x x x x x 0 0 0 cpu access r r r r r r/w r/w r/w note: r/w = read/write, r = read only. bit position v alue description [7:3] 00h reserved. [2:0] flash_row 0hC7h row address of flash memory to be used during an i/o write to flash memory. when info_en is 1 in the flash page select register, values for this field are restricted to 0hC1h, which selects between the two rows in the information page.
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 205 flash column select register the column select re gister is a 7-bit v alue used to de? ne one of the 128 bytes of flash memory on a single ro w . this re gister is used for all i/o write access to flash. this re gister must be set to the proper column location within a ro w to program using a single-byte write operation. in multibyte ro w programming, this re gister is used as the start address for the hardw are incrementer . flash program control register the flash program control re gister is used to perform the functions of mass erase, p age erase, and ro w program. mass erase and p age erase are self-clearing functions. mass erase requires approximately 200 ms to erase the full 128 kb/64 kb of main flash and the 256 byte information p age. p age erase requires approximately 10 ms to erase a 1 kb page. upon completion of either a mass erase or p age erase, the v alue of the corresponding bit is reset to 0. while flash is being erased, an y read or write access of flash memory force the cpu into a w ait state until the erase operation is complete and flash can be accessed. reads and writes to areas other than flash can proceed as usual while an erase operation is underw ay . during ro w programming, an y reads of flash memory force a w ait condition until the ro w programming operation completes or times out. t able 125. flash column select registe r ( flash_col= 00feh) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r/w r/w r/w r/w r/w r/w r/w note: r/w = read/write, r = read only. bit position v alue description [7] 0 reserved [6:0] flash_col 00hC 7fh column address within a row of flash memory to be used during an i/o write of flash memory.
ps015309-1004 preliminary flash memory ez80f92/ez80f93 product specification 206 t able 126. flash program control registe r ( flash_pgctl= 00ffh) bit 7 6 5 4 3 2 1 0 reset 0 0 0 0 0 0 0 0 cpu access r r r r r r/w r/w r/w note: r/w = read/write, r = read only. bit position v alue description [7:3] 0000 reserved. [2] row_pgm 0 row program disable or row program completed. 1 row program enable. this bit automatically resets to 0 when the row address reaches 128 or when the row program operation times out. [1] pg_erase 0 page erase disable (page erase completed) 1 page erase enable. this bit automatically resets to 0 when the page erase operation is complete. [0] mass_erase 0 mass erase disable (mass erase completed) 1 mass erase enable. this bit automatically resets to 0 when the mass erase operation is complete.
ps015309-1004 preliminary ez80 ? cpu instruction set ez80f92/ez80f93 product specification 207 ez80 ? cpu instruction set t ables 127 through 136 indicate the ez80 ? cpu instructions a v ailable for use with the ez80f92 de vice. the instructions are grouped by class. more detailed information is a v ail - able in the ez80 cpu user manual (um0077). t able 127. arithmetic instructions mnemonic instruction adc add with carry add add without carry cp compare with accumulator daa decimal adjust accumulator dec decrement inc increment mlt multiply neg negate accumulator sbc subtract with carry sub subtract without carry t able 128. bit manipulation instructions mnemonic instruction bit bit test res reset bit set set bit t able 129. block t ransfer and compare instructions mnemonic instruction cpd (cpdr) compare and decrement (with repeat) cpi (cpir) compare and increment (with repeat) ldd (lddr) load and decrement (with repeat) ldi (ldir) load and increment (with repeat)
ps015309-1004 preliminary ez80 ? cpu instruction set ez80f92/ez80f93 product specification 208 t able 130. exchange instructions mnemonic instruction ex exchange registers exx exchange cpu multibyte register banks t able 131. input/output instructions mnemonic instruction in input from i/o in0 input from i/o on page 0 ind (indr) input from i/o and decrement (with repeat) indrx input from i/o and decrement memory address with stationary i/o address ind2 (ind2r) input from i/o and decrement (with repeat) indm (indmr) input from i/o and decrement (with repeat) ini (inir) input from i/o and increment (with repeat) inirx input from i/o and increment memory address with stationary i/o address ini2 (ini2r) input from i/o and increment (with repeat) inim (inimr) input from i/o and increment (with repeat) otdm (otdmr) output to i/o and decrement (with repeat) otdrx output to i/o and decrement memory address with stationary i/o address otim (otimr) output to i/o and increment (with repeat) otirx output to i/o and increment memory address with stationary i/o address out output to i/o out0 output to i/o on page 0 outd (otdr) output to i/o and decrement (with repeat) outd2 (otd2r) output to i/o and decrement (with repeat) outi (otir) output to i/o and increment (with repeat) outi2 (oti2r) output to i/o and increment (with repeat) tstio test i/o
ps015309-1004 preliminary ez80 ? cpu instruction set ez80f92/ez80f93 product specification 209 t able 132. load instructions mnemonic instruction ld load lea load effective address pea push effective address pop pop push push t able 133. logical instructions mnemonic instruction and logical and cpl complement accumulator or logical or tst test accumulator xor logical exclusive or t able 134. processor control instructions mnemonic instruction ccf complement carry flag di disable interrupts ei enable interrupts halt halt im interrupt mode nop no operation rsmix reset mixed-memory mode flag scf set carry flag slp sleep stmix set mixed-memory mode flag
ps015309-1004 preliminary ez80 ? cpu instruction set ez80f92/ez80f93 product specification 210 t able 135. program control instructions mnemonic instruction call call subroutine call cc conditional call subroutine djnz decrement and jump if nonzero jp jump jp cc conditional jump jr jump relative jr cc conditional jump relative ret return ret cc conditional return reti return from interrupt retn return from nonmaskable interrupt rst restart t able 136. rotate and shift instructions mnemonic instruction rl rotate left rla rotate leftCaccumulator rlc rotate left circular rlca rotate left circularCaccumulator rld rotate left decimal rr rotate right rra rotate rightCaccumulator rrc rotate right circular rrca rotate right circularCaccumulator rrd rotate right decimal sla shift left arithmetic sra shift right arithmetic srl shift right logical
ps015309-1004 preliminary op-code map ez80f92/ez80f93 product specification 211 op-code map t ables 137 through 143 indicate the he x v alues for each of the ez80 ? cpu instructions. t able 137. op code mapfir st op code lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 nop ld bc, mmn ld (bc),a inc bc inc b dec b ld b,n rlca ex af ,af add hl,bc ld a,(bc) dec bc inc c dec c ld c,n rrca 1 djnz d ld de, mmn ld (de),a inc de inc d dec d ld d,n rla jr d add hl,de ld a,(de) dec de inc e dec e ld e,n rra 2 jr nz,d ld hl, mmn ld (mmn), hl inc hl inc h dec h ld h,n daa jr z,d add hl,hl ld hl, (mmn) dec hl inc l dec l ld l,n cpl 3 jr nc,d ld sp , mmn ld (mmn), a inc sp inc (hl) dec (hl) ld (hl),n scf jr cf ,d add hl,sp ld a, (mmn) dec sp inc a dec a ld a,n ccf 4 .sis suf fix ld b,c ld b,d ld b,e ld b,h ld b,l ld b,(hl) ld b,a ld c,b .lis suf fix ld c,d ld c,e ld c,h ld c,l ld c,(hl) ld c,a 5 ld d,b ld d,c .sil suf fix ld d,e ld d,h ld d,l ld d,(hl) ld d,a ld e,b ld e,c ld e,d .lil suf fix ld e,h ld e,l ld e,(hl) ld e,a 6 ld h,b ld h,c ld h,d ld h,e ld h,h ld h,l ld h,(hl) ld h,a ld l,b ld l,c ld l,d ld l,e ld l,h ld l,l ld l,(hl) ld l,a 7 ld (hl),b ld (hl),c ld (hl),d ld (hl),e ld (hl),h ld (hl),l hal t ld (hl),a ld a,b ld a,c ld a,d ld a,e ld a,h ld a,l ld a,(hl) ld a,a 8 add a,b add a,c add a,d add a,e add a,h add a,l add a,(hl) add a,a adc a,b adc a,c adc a,d adc a,e adc a,h adc a,l adc a,(hl) adc a,a 9 sub a,b sub a,c sub a,d sub a,e sub a,h sub a,l sub a,(hl) sub a,a sbc a,b sbc a,c sbc a,d sbc a,e sbc a,h sbc a,l sbc a,(hl) sbc a,a a and a,b and a,c and a,d and a,e and a,h and a,l and a,(hl) and a,a xor a,b xor a,c xor a,d xor a,e xor a,h xor a,l xor a,(hl) xor a,a b or a,b or a,c or a,d or a,e or a,h or a,l or a,(hl) or a,a cp a,b cp a,c cp a,d cp a,e cp a,h cp a,l cp a,(hl) cp a,a c ret nz pop bc jp nz, mmn jp mmn call nz, mmn push bc add a,n rst 00h ret z ret jp z, mmn t able 138 call z, mmn call mmn adc a,n rst 08h d ret nc pop de jp nc, mmn out (n),a call nc, mmn push de sub a,n rst 10h ret cf exx jp cf , mmn in a,(n) call cf , mmn t able 139 sbc a,n rst 18h e ret po pop hl jp po, mmn ex (sp),hl call po, mmn push hl and a,n rst 20h ret pe jp (hl) jp pe, mmn ex de,hl call pe, mmn t able 140 xor a,n rst 28h f ret p pop af jp p , mmn di call p , mmn push af or a,n rst 30h ret m ld sp ,hl jp m, mmn ei call m, mmn t able 141 cp a,n rst 38h notes: n = 8-bit data; mmn = 16- or 24-bit addr or data; d = 8-bit twos-complement displacement. and 4 a lower op code nibble mnemonic second operand upper op code nibble first operand a,h legend
ps015309-1004 preliminary op-code map ez80f92/ez80f93 product specification 212 t able 138. op code mapsecond op code after 0cbh lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 rlc b rlc c rlc d rlc e rlc h rlc l rlc (hl) rlc a rrc b rrc c rrc d rrc e rrc h rrc l rrc (hl) rrc a 1 rl b rl c rl d rl e rl h rl l rl (hl) rl a rr b rr c rr d rr e rr h rr l rr (hl) rr a 2 sla b sla c sla d sla e sla h sla l sla (hl) sla a sra b sra c sra d sra e sra h sra l sra (hl) sra a 3 srl b srl c srl d srl e srl h srl l srl (hl) srl a 4 bit 0,b bit 0,c bit 0,d bit 0,e bit 0,h bit 0,l bit 0,(hl) bit 0,a bit 1,b bit 1,c bit 1,d bit 1,e bit 1,h bit 1,l bit 1,(hl) bit 1,a 5 bit 2,b bit 2,c bit 2,d bit 2,e bit 2,h bit 2,l bit 2,(hl) bit 2,a bit 3,b bit 3,c bit 3,d bit 3,e bit 3,h bit 3,l bit 3,(hl) bit 3,a 6 bit 4,b bit 4,c bit 4,d bit 4,e bit 4,h bit 4,l bit 4,(hl) bit 4,a bit 5,b bit 5,c bit 5,d bit 5,e bit 5,h bit 5,l bit 5,(hl) bit 5,a 7 bit 6,b bit 6,c bit 6,d bit 6,e bit 6,h bit 6,l bit 6,(hl) bit 6,a bit 7,b bit 7,c bit 7,d bit 7,e bit 7,h bit 7,l bit 7,(hl) bit 7,a 8 res 0,b res 0,c res 0,d res 0,e res 0,h res 0,l res 0,(hl) res 0,a res 1,b res 1,c res 1,d res 1,e res 1,h res 1,l res 1,(hl) res 1,a 9 res 2,b res 2,c res 2,d res 2,e res 2,h res 2,l res 2,(hl) res 2,a res 3,b res 3,c res 3,d res 3,e res 3,h res 3,l res 3,(hl) res 3,a a res 4,b res 4,c res 4,d res 4,e res 4,h res 4,l res 4,(hl) res 4,a res 5,b res 5,c res 5,d res 5,e res 5,h res 5,l res 5,(hl) res 5,a b res 6,b res 6,c res 6,d res 6,e res 6,h res 6,l res 6,(hl) res 6,a res 7,b res 7,c res 7,d res 7,e res 7,h res 7,l res 7,(hl) res 7,a c set 0,b set 0,c set 0,d set 0,e set 0,h set 0,l set 0,(hl) set 0,a set 1,b set 1,c set 1,d set 1,e set 1,h set 1,l set 1,(hl) set 1,a d set 2,b set 2,c set 2,d set 2,e set 2,h set 2,l set 2,(hl) set 2,a set 3,b set 3,c set 3,d set 3,e set 3,h set 3,l set 3,(hl) set 3,a e set 4,b set 4,c set 4,d set 4,e set 4,h set 4,l set 4,(hl) set 4,a set 5,b set 5,c set 5,d set 5,e set 5,h set 5,l set 5,(hl) set 5,a f set 6,b set 6,c set 6,d set 6,e set 6,h set 6,l set 6,(hl) set 6,a set 7,b set 7,c set 7,d set 7,e set 7,h set 7,l set 7,(hl) set 7,a notes: n = 8-bit data; mmn = 16- or 24-bit addr or data; d = 8-bit twos-complement displacement. res 4 a lower nibble of 2nd op code mnemonic second operand upper op code first operand 4,h of second nibble legend
ps015309-1004 preliminary op-code map ez80f92/ez80f93 product specification 213 t able 139. op code mapsecond op code after 0ddh lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 ld bc, (ix+d) add ix,bc ld (ix+d), bc 1 ld de, (ix+d) add ix,de ld (ix+d), de 2 ld ix, mmn ld (mmn), ix inc ix inc ixh dec ixh ld ixh,n ld hl, (ix+d) add ix,ix ld ix, (mmn) dec ix inc ixl dec ixl ld ixl,n ld (ix+d), hl 3 ld iy , (ix+d) inc (ix+d) dec (ix+d) ld (ix +d),n ld ix, (ix+d) add ix,sp ld (ix+d), iy ld (ix+d), ix 4 ld b,ixh ld b,ixl ld b, (ix+d) ld c,ixh ld c,ixl ld c, (ix+d) 5 ld d,ixh ld d,ixl ld d, (ix+d) ld e,ixh ld e,ixl ld e, (ix+d) 6 ld ixh,b ld ixh,c ld ixh,d ld ixh,e ld ixh,ixh ld ixh,ixl ld h, (ix+d) ld ixh,a ld ixl,b ld ixl,c ld ixl,d ld ixl,e ld ixl,ixh ld ixl,ixl ld l, (ix+d) ld ixl,a 7 ld (ix+d),b ld (ix+d),c ld (ix+d),d ld (ix+d),e ld (ix+d),h ld (ix+d),l ld (ix+d),a ld a,ixh ld a,ixl ld a, (ix+d) 8 add a,ixh add a,ixl add a, (ix+d) adc a,ixh adc a,ixl adc a, (ix+d) 9 sub a,ixh sub a,ixl sub a, (ix+d) sbc a,ixh sbc a,ixl sbc a, (ix+d) a and a,ixh and a,ixl and a, (ix+d) xor a,ixh xor a,ixl xor a, (ix+d) b or a,ixh or a,ixl or a, (ix+d) cp a,ixh cp a,ixl cp a, (ix+d) c t able 142 d e pop ix ex (sp),ix push ix jp (ix) f ld sp ,ix notes: n = 8-bit data; mmn = 16- or 24-bit addr or data; d = 8-bit twos-complement displacement. ld 9 f mnemonic second operand first operand sp,ix lower nibble of 2nd op code upper op code of second nibble legend
ps015309-1004 preliminary op-code map ez80f92/ez80f93 product specification 214 t able 140. op code mapsecond op code after 0edh lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 in0 b,(n) out0 (n),b lea bc, ix+d lea bc, iy+d tst a,b ld bc, (hl) in0 c,(n) out0 (n),c tst a,c ld (hl), bc 1 in0 d,(n) out0 (n),d lea de, ix+d lea de, iy+d tst a,d ld de, (hl) in0 e,(n) out0 (n),e tst a,e ld(hl), de 2 in0 h,(n) out0 (n),h lea hl ,ix+d lea hl ,iy+d tst a,h ld hl, (hl) in0 l,(n) out0 (n),l tst a,l ld (hl), hl 3 ld iy , (hl) lea ix ,ix+d lea iy ,iy+d tst a,(hl) ld ix, (hl) in0 a,(n) out0 (n),a tst a,a ld (hl),iy ld (hl), ix 4 in b,(bc) out (bc),b sbc hl,bc ld (mmn), bc neg retn im 0 ld i,a in c,(c) out (c),c adc hl,bc ld bc, (mmn) ml t bc reti ld r,a 5 in d,(bc) out (bc),d sbc hl,de ld (mmn), de lea ix, iy+d lea iy , ix+d im 1 ld a,i in e,(c) out (c),e adc hl,de ld de, (mmn) ml t de im 2 ld a,r 6 ibn h,(c) out (bc),h sbc hl,hl ld (mmn), hl tst a,n pea ix+d pea iy+d rrd in l,(c) out (c),l adc hl,hl ld hl, (mmn) ml t hl ld mb,a ld a,mb rld 7 sbc hl,sp ld (mmn), sp tstio n slp in a,(c) out (c),a adc hl,sp ld sp , (mmn) ml t sp stmix rsmix 8 inim otim ini2 indm otdm ind2 9 inimr otimr ini2r indmr otdmr ind2r a ldi cpi ini outi outi2 ldd cpd ind outd outd2 b ldir cpir inir otir oti2r lddr cpdr indr otdr otd2r c inirx otirx indrx otdrx d e f notes: n = 8-bit data; mmn = 16- or 24-bit addr or data; d = 8-bit twos-complement displacement. sbc 2 4 mnemonic second operand first operand hl,bc lower nibble of 2nd op code upper op code of second nibble legend
ps015309-1004 preliminary op-code map ez80f92/ez80f93 product specification 215 t able 141. op code mapsecond op code after 0fdh lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 ld bc, (iy+d) add iy ,bc ld (iy +d),bc 1 ld de, (iy+d) add iy ,de ld (iy +d),de 2 ld iy ,mmn ld (mmn),i y inc iy inc iyh dec iyh ld iyh,n ld hl, (iy+d) add iy ,iy ld iy , (mmn) dec iy inc iyl dec iyl ld iyl,n ld (iy +d),hl 3 ld ix, (iy+d) inc (iy+d) dec (iy+d) ld (iy +d),n ld iy , (iy+d) add iy ,sp ld (iy +d),ix ld (iy +d),iy 4 ld b,iyh ld b,iyl ld b, (iy+d) ld c,iyh ld c,iyl ld c, (iy+d) 5 ld d,iyh ld d,iyl ld d, (iy+d) ld e,iyh ld e,iyl ld e, (iy+d) 6 ld iyh,b ld iyh,c ld iyh,d ld iyh,e ld iyh,iyh ld iyh,iyl ld h, (iy+d) ld iyh,a ld iyl,b ld iyl,c ld iyl,d ld iyl,e ld iyl,iyh ld iyl,iyl ld l, (iy+d) ld iyl,a 7 ld (iy +d),b ld (iy +d),c ld (iy +d),d ld (iy +d),e ld (iy +d),h ld (iy +d),l ld (iy +d),a ld a,iyh ld a,iyl ld a, (iy+d) 8 add a,iyh add a,iyl add a, (iy+d) adc a,iyh adc a,iyl adc a, (iy+d) 9 sub a,iyh sub a,iyl sub a, (iy+d) sbc a,iyh sbc a,iyl sbc a, (iy+d) a and a,iyh and a,iyl and a, (iy+d) xor a,iyh xor a,iyl xor a, (iy+d) b or a,iyh or a,iyl or a, (iy+d) cp a,iyh cp a,iyl cp a, (iy+d) c t able 143 d e pop iy ex (sp),iy push iy jp (iy) f ld sp ,iy notes: n = 8-bit data; mmn = 16- or 24-bit addr or data; d = 8-bit twos-complement displacement. ld 9 f mnemonic second operand first operand sp,iy lower nibble of 2nd op code upper op code of second nibble legend
ps015309-1004 preliminary op-code map ez80f92/ez80f93 product specification 216 t able 142. op code mapfourth byte after 0ddh, 0cbh, and dd lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 rlc (ix+d) rrc (ix+d) 1 rl (ix+d) rr (ix+d) 2 sla (ix+d) sra (ix+d) 3 srl (ix+d) 4 bit 0, (ix+d) bit 1, (ix+d) 5 bit 2, (ix+d) bit 3, (ix+d) 6 bit 4, (ix+d) bit 5, (ix+d) 7 bit 6, (ix+d) bit 7, (ix+d) 8 res 0, (ix+d) res 1, (ix+d) 9 res 2, (ix+d) res 3, (ix+d) a res 4, (ix+d) res 5, (ix+d) b res 6, (ix+d) res 7, (ix+d) c set 0, (ix+d) set 1, (ix+d) d set 2, (ix+d) set 3, (ix+d) e set 4, (ix+d) set 5, (ix+d) f set 6, (ix+d) set 7, (ix+d) notes: d = 8-bit twos-complement displacement. bit 6 4 lower nibble of 4th byte mnemonic second operand upper byte first operand 0,(ix+d) of fourth nibble legend
ps015309-1004 preliminary op-code map ez80f92/ez80f93 product specification 217 t able 143. op code mapfourth byte after 0fdh, 0cbh, and dd* lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f upper nibble (hex) 0 rlc (iy+d) rrc (iy+d) 1 rl (iy+d) rr (iy+d) 2 sla (iy+d) sra (iy+d) 3 srl (iy+d) 4 bit 0, (iy+d) bit 1, (iy+d) 5 bit 2, (iy+d) bit 3, (iy+d) 6 bit 4, (iy+d) bit 5, (iy+d) 7 bit 6, (iy+d) bit 7, (iy+d) 8 res 0, (iy+d) res 1, (iy+d) 9 res 2, (iy+d) res 3, (iy+d) a res 4, (iy+d) res 5, (iy+d) b res 6, (iy+d) res 7, (iy+d) c set 0, (iy+d) set 1, (iy+d) d set 2, (iy+d) set 3, (iy+d) e set 4, (iy+d) set 5, (iy+d) f set 6, (iy+d) set 7, (iy+d) notes: d = 8-bit twos-complement displacement. bit 6 4 lower nibble of 4th byte mnemonic second operand upper byte first operand 0,(iy+d) of fourth nibble legend
ps015309-1004 preliminary on-chip oscillators ez80f92/ez80f93 product specification 218 on-chip oscillators the ez80f92 de vice features tw o on-chip oscillators for use with an e xternal crystal. the primary oscillator generates the system clock for the internal cpu and the majority of the on-chip peripherals. alternati v ely , the x in input pin can also accept a cmos-le v el clock input signal. if an e xternal clock generator is used, the x out pin should be left uncon - nected. the secondary oscillator can dri v e a 32 khz crystal to generate the time-base for the real-t ime clock. 20 mhz primary crystal oscillator operation figure 50 illustrates a recommended con? guration for connection with an e xternal 20mhz, fundamental-mode, parallel-resonant crystal. recommended crystal speci? ca - tions are pro vided in t able 144 . resistor r 1 limits total po wer dissipation by the crystal. printed circuit board layout should add no more than 4pf of stray capacitance to either the x in or x out pins. if oscillation does not occur , reduce the v alues of capacitors c 1 a nd c 2 to decrease loading. figure 50. recommended crystal oscillator configuration (20mhz operation) x c = 22 pf in x out 2 r = 220 ? 1 r = 100 k? 2 c = 22 pf 2 20 mhz crystal (fundamental mode) on-chip oscillator
ps015309-1004 preliminary on-chip oscillators ez80f92/ez80f93 product specification 219 32 khz real-time clock crystal oscillator operation figure 51 illustrates a recommended con? guration for connecting the real-t ime clock oscillator with an e xternal 32 khz, fundamental-mode, parallel-resonant crystal. the rec - ommended crystal speci? cations are pro vided in t able 145 . a printed circuit board layout should add no more than 4 pf of stray capacitance to either the r tc_x in or r tc_x out pins. if oscillation does not occur , reduce the v alues of capacitors c 1 and c 2 to decrease loading. an on-chip mos resistor sets the crystal dri v e current limit. this con? guration does not require an e xternal bias resistor across the crystal. an on-chip mos resistor pro vides the biasing. t able 144. recommended crystal oscillator specification s ( 20 mhz operation) parameter v alue units comments frequency 20 mhz resonance parallel mode fundamental series resistance (r s ) 25 ? maximum load capacitance (c l ) 20 pf maximum shunt capacitance (c 0 ) 7 pf maximum drive level 1 m? maximum figure 51. recommended crystal oscillator configuration (32khz operation) r tc_x c = 18 pf in r tc_x out 2 r = 220 ? 1 c = 18 pf 2 32 mhz crystal (fundamental mode) on-chip oscillator
ps015309-1004 preliminary on-chip oscillators ez80f92/ez80f93 product specification 220 t able 145. recommended crystal oscillator specification s ( 32 khz operation) parameter v alue units comments frequency 32 khz 32768 hz resonance parallel mode fundamental series resistance (r s ) 40 k? maximum load capacitance (c l ) 12.5 pf maximum shunt capacitance (c 0 ) 3 pf maximum drive level 1 ? maximum
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 221 electrical characteristics absolute maximum ratings stresses greater than those listed in t able 146 may cause permanent damage to the de vice. these ratings are stress ratings only . operation of the de vice at an y condition outside those indicated in the operational sections of these speci? cations is not implied. exposure to absolute maximum rating conditions for e xtended periods may af fect de vice reliability . f or impro v ed reliability , unused inputs should be tied to one of the supply v oltages ( v dd or v ss ). dc characteristics t able 147 lists the dc characteristics of the ez80f92 de vice. all data is preliminary and subject to change follo wing completion of production characterization. t able 146. absolute maximum ratings parameter min max units notes ambient temperature under bias (oc) C40 +105 c 1 storage temperature (oc) C65 +150 c voltage on any pin with respect to v ss C0.3 +5.5 v 2 voltage on v dd pin with respect to v ss C0.3 +3.6 v total power dissipation 520 mw maximum current out of v ss 145 ma maximum current into v dd 145 ma maximum current on input and/or inactive output pin C25 +25 a maximum output current from active output pin C8 +8 ma notes: 1. operating temperature is specified in dc characteristics. 2. this voltage applies to all pins except where noted otherwise. note:
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 222 t able 147. dc characteristics symbol parameter t a = 0oc to 70oc t a = 0oc to 105oc units conditions min max min max v dd supply voltage 3.0 3.6 3.0 3.6 v v il low level input voltage C0.3 0.8 C0.3 0.8 v v ih high level input voltage 0.7 x v dd 5.5 0.7 x v dd 5.5 v v ol low level output voltage 0.4 0.4 v v dd = 3.0 v; i ol = 1 ma v oh high level output voltage 2.4 2.4 v v dd = 3.0 v; i oh = C1 ma i il input leakage current C10 +10 C20 +20 a v dd = 3.6v; v in = v dd or v ss 1 i tl tristate leakage current C10 +10 C20 +20 a v dd = 3.6 v i pu internal pull-up current 100 t ypical 100 t ypical a v dd = 3.6 v; 25oc i dd power dissipation (normal operation) 33 t ypical 33 t ypical ma f = 20 mhz; v dd = 3.3v; 7 wait states; 25oc power dissipation ( halt mode) 21 t ypical 21 t ypical ma f = 20 mhz; v dd = 3.3v; 25oc power dissipation ( sleep mode) 375 t ypical 600 t ypical a v dd = 3.3v; 25oc rtc_v dd rtc supply voltage 3.0 3.6 3.0 3.6 v i rtc rtc supply current 2.5 10 t ypical 2.5 10 t ypical a supply current into rtc_v dd ; sleep mode 2 . notes: 1. this condition excludes all pins with on-chip pull-ups when driven low . 2. r tc current increases when the ez80f92 device is not in sleep mode as the r tc_vdd pin supplies power to system clock buf fers within the real-t ime clock circuit.
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 223 por and vbo electrical characteristics t able 147 lists the po wer -on reset and v oltage bro wn-out characteristics of the ez80f92 de vice. typical current consumption under various operating conditions in the follo wing pages, figure 52 illustrates the typical current consumption of the ez80f92 de vice v ersus the number of w ait states while operating 25 oc, 3.3v , and with either a 1 mhz, 10 mhz, 15 mhz or 20 mhz system clock. figure 53 illustrates the typical current consumption of the ez80f92 de vice v ersus the system clock frequenc y while oper - ating 25 oc, 3.3v , and using 0, 2, or 7 w ait states. figure 54 illustrates the typical current consumption of the ez80f92 de vice v ersus temperature while operating at 3.3v , 7 w ait states, and with either a 1 mhz, 10 mhz, 15 mhz or 20 mhz system clock. figure 55 illus - trates the typical current consumption of the ez80f92 de vice v ersus system clock fre - quenc y while operating in hal t mode. figure 56 illustrates the typical current consumption of the ez80f92 de vice v ersus temperature while operating in sleep mode. t able 148. por and vbo electrical characteristics symbol parameter t a = 0oc to +105oc unit conditions min t yp max v vbo vbo voltage threshold 2.40 2.55 2.85 v v cc = v vbo v por por voltage threshold 2.45 2.65 2.90 v v cc = v por . v hyst por/vbo hysteresis 50 100 150 mv t ana por/vbo analog reset duration 40 100 s t vbo_min vbo pulse reject period 10 s v cc ramp v cc ramp rate requirements to guarantee proper reset occurs 0.1 100 v/ms
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 224 figure 52. i cc v ersus w ait states as a function of frequency i cc vs. wait states (typical @ 3.3v, 25c) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 0123456 7 wait states current (ma) 5 mhz 10 mhz 15 mhz 20 mhz
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 225 figure 53. i cc v ersus frequency as a function of w ait states i cc vs. frequency (typical @3.3v, 25c) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 5101 520 frequency (mhz) current (ma) 0 wait 2 wait 7 wait
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 226 figure 54. i cc v ersus t emperature as a function of frequency i cc versus temp with 7 wait states (typical @ 3.3v) 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 020406 080 100 temperature (c) current (ma) 5 mhz 10 mhz 15 mhz 20 mhz
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 227 figure 55. i cc v ersus frequency in hal t mode i cc vs. frequency in halt mode (typical @ 3.3v) 0 5 10 15 20 25 0510 15 20 frequency (mhz) current (ma)
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 228 ac characteristics the section pro vides information about t he a c characteristics and timing of the ez80f92 de vice. all a c timing information assumes a standard load of 50 pf on all outputs. see t able 149 . all data is preliminary and subject to change follo wing completion of production characterization. figure 56. i cc v ersus t emperature in sleep mode i cc vs. temperature in sleep mode (typical @ 3.3v, rtc operating at 32khz) 0 50 100 150 200 250 300 350 400 450 020406 080 100 temperature (c) current (ua) note:
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 229 external memory read timing figure 57 and t able 150 diagram the timing for e xternal reads. t able 149. ac characteristics symbol parameter t a = 0oc to 70oc t a = 0oc to 105oc units conditions min max min max t xin system clock cycle time 50 50 ns v dd = 3.0C3.6v t xinh system clock high time 20 20 ns v dd = 3.0C3.6v; t clk = 50ns t xinl system clock low time 20 20 ns v dd = 3.0C3.6v; t clk = 50ns t xinr system clock rise time 3 3 ns v dd = 3.0C3.6v; t clk = 50ns t xinf system clock fall time 3 3 ns v dd = 3.0C3.6v; t clk = 50ns figure 57. external memory read t iming x addr[23:0] data[7:0] (input) csx mreq rd in t 1 t 2 t 3 t 4 t 8 t 6 t 10 t 7 t 5 t 9 t clk
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 230 external memory write timing figure 58 and t able 151 diagram the timing for e xternal writes. t able 150. external read t iming parameter abbreviation delay (ns) min max t 1 clock rise to addr valid delay 13 t 2 clock rise to addr hold time 2.0 t 3 input data valid to clock rise setup time 1.0 t 4 clock rise to data hold time 2.0 t 5 clock rise to csx assertion delay 2.0 19.0 t 6 clock rise to csx deassertion delay 2.0 18.0 t 7 clock rise to mreq assertion delay 2.0 16.0 t 8 clock rise to mreq deassertion delay 2.0 16.0 t 9 clock rise to rd assertion delay 2.0 16.0 t 10 clock rise to rd deassertion delay 2.0 16.0 figure 58. external memory w rite t iming x addr[23:0] data[7:0] (output) csx mreq wr in t 1 t 2 t 3 t 4 t 8 t 6 t 10 t 7 t 5 t 9 t clk
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 231 t able 151. external w rite t iming parameter abbreviation delay (ns) min max t 1 clock rise to addr valid delay 13 t 2 clock rise to addr hold time 2.0 t 3 clock fall to output data valid delay 11 t 4 clock rise to data hold time 2.0 t 5 clock rise to csx assertion delay 2.0 19.0 t 6 clock rise to csx deassertion delay 2.0 18.0 t 7 clock rise to mreq assertion delay 2.0 16.0 t 8 clock rise to mreq deassertion delay 2.0 16.0 t 9 clock fall to wr assertion delay 1.8 6.5 t 10 clock rise to wr deassertion delay* 1.6 6.5 wr deassertion to addr hold time 0.25 wr deassertion to data hold time 0.25 wr deassertion to csx hold time 0.25 wr deassertion to mreq hold time 0.25 note: *at the conclusion of a write cycle, deassertion of wr always occurs before any change to addr, data, csx , or mreq .
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 232 external i/o read timing figure 59 and t able 152 diagram the timing for e xternal i/o reads. clock rise/f all to sig - nal transition timing is independent of the particular b us mode emplo yed (ez80, z80, intel tm , or motorola). figure 59. external i/o read t iming t able 152. external i/o read t iming parameter abbreviation delay (ns) min max t 1 clock rise to addr valid delay 13 t 2 clock rise to addr hold time 2.0 t 3 input data valid to clock rise setup time 1.0 t 4 clock rise to data hold time 2.0 t 5 clock rise to csx assertion delay 2.0 19.0 t 6 clock rise to csx deassertion delay 2.0 18.0 t 7 clock rise to iorq assertion delay 2.0 16.0 t 8 clock rise to iorq deassertion delay 2.0 16.0 t 9 clock rise to rd assertion delay 2.0 16.0 t 10 clock rise to rd deassertion delay 2.0 16.0 x addr[23:0] data[7:0] (input) csx iorq rd in t 1 t 2 t 3 t 4 t 8 t 6 t 10 t 7 t 5 t 9 t clk
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 233 external i/o write timing figure 60 and t able 153 diagram the timing for e xternal i/o writes. clock rise/f all to sig - nal transition timing is independent of the particular b us mode emplo yed (ez80, z80, intel tm , or motorola). figure 60. external i/o w rite t iming t able 153. external i/o w rite t iming parameter abbreviation delay (ns) min max t 1 clock rise to addr valid delay 13 t 2 clock rise to addr hold time 2.0 t 3 clock fall to output data valid delay 11 t 4 clock rise to data hold time 2.0 t 5 clock rise to csx assertion delay 2.0 19.0 t 6 clock rise to csx deassertion delay 2.0 18.0 t 7 clock rise to iorq assertion delay 2.0 16.0 t 8 clock rise to iorq deassertion delay 2.0 16.0 note: *at the conclusion of a write cycle, deassertion of wr always occurs before any change to addr, data, csx , or iorq . x addr[23:0] data[7:0] (output) csx iorq wr in t 1 t 2 t 3 t 4 t 8 t 6 t 10 t 7 t 5 t 9 t clk
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 234 wait state timing for read operations figure 61 illustrates the e xtension of the memory access signals using a single w ait state for a read operation. this w ait state is generated by setting cs_w ait to 001h in the chip select control re gister . t 9 clock fall to wr assertion delay 1.8 6.5 t 10 clock rise to wr deassertion delay* 1.6 6.5 wr deassertion to addr hold time 0.25 wr deassertion to data hold time 0.25 wr deassertion to csx hold time 0.25 wr deassertion to iorq hold time 0.25 figure 61. w ait state t iming for read operations t able 153. external i/o w rite t iming (continued) parameter abbreviation delay (ns) min max note: *at the conclusion of a write cycle, deassertion of wr always occurs before any change to addr, data, csx , or iorq . t clk t wait x addr[23:0] data[7:0] (output) csx mreq rd in instrd
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 235 wait state timing for write operations figure 62 illustrates the e xtension of the memory access signals using a single w ait state for a write operation. this w ait state is generated by setting cs_w ait to 001h in the chip select control re gister . figure 62. w ait state t iming for w rite operations t clk t wait x addr[23:0] data[7:0] (output) csx mreq wr in
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 236 general purpose i/o port input sample timing figure 63 illustrates timing of the gpio input sampling. the input v alue on a gpio port pin is sampled on the rising edge of the system clock. the port v alue is then a v ailable to the cpu on the second rising clock edge follo wing the change of the port v alue. figure 63. port input sample t iming t able 154. gpio port output t iming parameter abbreviation delay (ns) min max t 1 clock rise to port output delay 2.0 15.0 t clk system clock gpio pin input value gpio input data latch gpio data read on data bus port value changes to 0 0 latched into gpio data register gpio data register v alue 0 read by ez80
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 237 external bus acknowledge timing t able 155 pro vides information about t he b us ackno wledge timing. once the e xternal b us master detects b usa ck asserted and dri v es iorqn, mreqn, a[23:0] there is an asyn - chronous prop delay to the cs[3:0] outputs being v alid. external system clock driver (phi) timing t able 156 pro vides timing information for the phi pin. the phi pin allo ws e xternal peripherals to synchronize with the internal system clock dri v er on the ez80f92 de vice. t able 155. bus acknowledge t iming parameter abbreviation delay (ns) min max t 1 clock rise to busack assertion delay 2.0 14.0 t 2 clock rise to busack deassertion delay 2.0 14.0 t 3 iorqn, mreqn, a[23:0] input to cs[3:0] output prop delay 10.0 t able 156. phi system clock t iming parameter abbreviation delay (ns) min max t 1 clock (xin) rise to phi rise 6.0 t 2 clock (xin) fall to phi fall 6.0
ps015309-1004 preliminary electrical characteristics ez80f92/ez80f93 product specification 238 zilog debug interface timing figure 64 and t able 157 pro vide timing information for tck, tdi, tdo, tms pins. figure 64. zdi t iming t able 157. zdi t iming specifications parameter abbreviation delay (ns) min max t tck tck period 2 x t xin t 1 tdi/tms setup to tck rise 4 t 2 tdi/tms hold after tck rise fall 4 t 3 tck rise to tdo change 10 t1 t2 t3 tck tdi tms tdo
ps015309-1004 preliminary packaging ez80f92/ez80f93 product specification 239 packaging figure 65 illustrates the 100-pin lo w-pro? le quad ? at package (lqfp) for the ez80f92 de vice. figure 65. 100-lead plastic low-profile quad flat package (lqfp)
ps015309-1004 preliminary ordering information ez80f92/ez80f93 product specification 240 ordering information t able 158 pro vides a part name, a product speci? cation inde x code, and a brief description of each part. na vig ate your bro wser to zilog s website to order the ez80f92 or the ez80f93 . or , con - tact your local zilog sales of ? ce to order these de vices. zilog pro vides additional assistance on its customer service page, and is also here to help with technical support issues. f or zilog s v aluable softw are de v elopment tools and do wnloadable softw are , visit the zilog website . part number description zilog part numbers consist of a number of components, as indicated in the follo wing e xamples: t able 158. ordering information part name psi description ez80f92 ez80f92az020sc , ez80f92az020sg 100-pin lqfp, 128 kb flash memory, 8 kb sram, 20 mhz, standard temperature. EZ80F92AZ020EC , ez80f92az020eg 100-pin lqfp, 128 kb flash memory, 8 kb sram, 20 mhz, extended temperature. ez80f93 ez80f93az020sc , ez80f93az020sg 100-pin lqfp, 64 kb flash memory, 4 kb sram, 20 mhz, standard temperature. ez80f93az020ec , ez80f93az020eg 100-pin lqfp, 64 kb flash memory, 4 kb sram, 20 mhz, extended temperature. zilog base products ez80 zilog ez80 ? cpu f92 product number az package 020 speed s or e temperature c or g environmental flow
ps015309-1004 preliminary ordering information ez80f92/ez80f93 product specification 241 example . p art number ez80f92az020sc is an ez80acclaim! ? product in an lqfp package, operating with a 20 mhz e xternal clock frequenc y o v er a 0oc to +70oc tempera - ture range and b uilt using the plastic standard en vironmental ? o w . precharacterization product the product represented by this document is ne wly introduced and zilog has not com - pleted the full characterization of the product. the document states what zilog kno ws about this product at this time, b ut additional features or nonconformance with some aspects of the document might be found, either by zilog or its customers in the course of further application and characterization w ork. in addition, zilog cautions that deli v ery might be uncertain at times, due to start-up yield issues. zilog, inc. 532 race street san jose, ca 95126 t elephone (408) 558-8500 f ax 408 558-8300 internet: www .zilog.com package az = lqfp (also called the vqfp) speed 020 = 20 mhz standard temperature s = 0oc to +70oc extended temperature e = C40oc to +105oc environmental flow c = plastic standard; g = lead-free
ps015309-1004 preliminary document information ez80f92/ez80f93 product specification 242 document information document number description the document control number that appears in the footer on each page of this document contains unique identifying attrib utes, as indicated in the follo wing table: change log ps product specification 0153 unique document number 08 revision number 0404 month and year published rev date purpose by 01 06/02 original issue j. eversmann/r. beebe 02 01/03 technical updates j. eversmann 03 01/03 technical updates m. richmond, r. beebe 04 02/03 modified hyperlinks/refs. a. abuhakmeh, a. koontz 05 08/03 modified extended temp. r. xue, a. shaw 06 08/03 minor revision r. beebe 07 02/04 revised brg in uart section c. bender 08 04/04 added cautions for slp/hlt c. bender
ez80f92/ez80f93 product specification ps015309-1004 preliminary index 243 index numerics 100-pin lqfp package 4 , 20 16-bit clock divisor value 110 , 135 16-bit divisor count 110 , 135 20 mhz primary crystal oscillator operation 218 32 khz real-time clock crystal oscillator opera - tion 219 a aak see i 2 c acknowledge bit a bsolute maximum ratings 22 1 a c characteristics 228 ack see acknowledge acknowledge 142 , 146 C 150 , 152 , 157 a ddress bus 5 C9 , 47 , 51 , 53 C 5 8 , 61 , 64 C 6 5 , 68 C 6 9 , 90 , 168 , 178 , 184 address bus, 24-bit 24 addressing 152 adl memory mode 180 , 18 4 a larm condition 89 , 102 , 10 3 a rbitration 144 architectural overview 1 asynchronous serial data 12 , 15 b baud rate generator 109 control registers 110 f unctional description 134 bcdsee binary-coded-decimal operation binary-coded-decimal operation 88 , 90 C 103 b it generation 104 block diagram 2 boundary-scan architecture 186 break detection 104 , 113 break point trigger functions 18 6 b us acknowledge 11 , 22 , 53 , 168 , 178 , 184 , 237 p in 53 , 178 bus arbitration overview 140 bus enable bit 154, 156 bus mode controller 54 bus mode state 54 C 5 5 , 58 , 62 , 66 , 72 bus modes 54, 6 7, 7 1 bus request 11 , 22 , 53 , 168 , 178 , 184 d uring zdi debug mode 168 busack see bus acknowledge busreq see bus request byte format 142 c change log 242 characteristics, electrical absolute maximum ratings 221 chip select 0 9 chip select 1 9 chip select 2 9 chip select 3 9 chip select registers 68 chip select x bus mode control register 71 chip select x control register 70 chip select x lower bound register 68 chip select x upper bound register 69 chip select/wait state generator block 5 , 6 , 7 , 8 , 9 chip selects and wait states 49 chip selects during bus request/bus acknowl - edge cycles 53 clear to send 13 , 16 , 119 , 122 clock divisor value, 16-bit 110 , 135 clock initialization circuitry 186 clock peripheral power-down registers 37 clock phase bit 131 C 133 , 137 clock polarity bit 132C 133 , 137 c lock synchronization 143 clocking overview 140 complex triggers 186 continuous mode 77 , 79 C 8 3 , 85 C 8 6 cpha see clock phase bit c pol see clock polarity bit
ez80f92/ez80f93 product specification ps015309-1004 preliminary index 244 c pu system clock cycle 55 cs0 9 , 21 , 49 C 5 2 cs1 9 , 21 , 49 C 5 2 cs2 9 , 21 , 49 , 51 C 5 2 cs3 9 , 21 , 49 , 51 C 5 2 cts see clear to send cts0 13 , 128 cts1 16 customer feedback form 253 cycle termination signal 65 d d ata bus 9, 53 C 5 4 , 56 C 5 8 , 61, 65 , 71 , 90 , 168 , 178 , 184 data carrier detect 14 , 16 , 119 , 122 delta change status of 122 d ata set ready 14 , 16 , 119 , 122 delta change status of 122 data terminal ready 14 , 16 , 119 , 122 delta change status of 122 data transfer procedure with spi configured as a slave 135 data transfer procedure with spi configured as the master 134 data transfer, spi 138 data validity 141 dc characteristics 221 dcd see data carrier detect dcd0 14 , 128 dcd1 16 dcts 122 ddcd see data carrier detect, delta change status of ddsr see data set ready, delta change status of ddtrsee data terminal ready, delta change status of d ivisor count 110 , 135 document information 242 document number description 242 dsr see data set ready dsr0 14 , 128 dsr1 16 dtack see cycle termination signal dtr see data terminal ready dtr0 14 , 128 dtr1 16 e edge-selectable interrupts 44 edge-triggered interrupt input 128 edge-triggered interrupt mode 42 , 44 edge-triggered interrupts 43 ei, op code map 211 electrical characteristics 22 1 e nabling and disabling the wdt 74 enabsee bus enable bi t e ndecsee infrared encoder/decoder 38 , 124 C 125 , 128C 129 erase operations 192 C 1 93 event counter 81 external bus acknowledge timing 237 external bus request 53 , 164 , 168 external i/o chip selects 24 external i/o read timing 232 external i/o write timing 233 external memory read timing 229 external memory write timing 230 external pull-down resistor 41 external system clock driver (phi) timing 237 ez80 bus mode 54 , 67 , 71 e z80 cpu 10 , 36 , 53 , 57 , 58 , 65 , 170 , 186 c ore 32 i nstruction set 207 ez80 product id low and high byte registers 181 ez80 product id revision register 18 2 ez80 ? s ystem clock cycle 54 C 5 5 , 58 , 61 ez80f92 3 , 73 , 170 , 182 ez80f92 processor 1 C 2, 4 C 5 , 9 , 24 , 36 , 40 , 46 , 47 C 4 9 , 51 , 67 , 77 , 81 , 108 C 1 09 , 152 , 162 C 1 64 , 166 , 174 C 1 75 , 179 , 180 , 184 , 218 , 221 , 223 , 228 , 23 7 f f ast mode 140 , 16 0 f eatures, ez80 cpu core 32
ez80f92/ez80f93 product specification ps015309-1004 preliminary index 245 flash memory 190 , 19 2 a rrangement in the ez80f93 193 o verview 193 framing error 104 , 106 , 113 full-duplex transmission 133 functional description, infrared encoder/decoder 124 g g eneral-purpose input/output 4 0 control registers 44 interrupts 43 modes 41 C 42 operation 40 overview 40 port input sample timing 236 port output timing 238 port pins 33 , 40 , 45 gnd see ground gpiosee general-purpose input/output ground 2 h h alt instruction 36 , 174 , 182 , 209 h alt mode 1 , 11 , 36 C 3 7 , 222 , 223 , 227 halt, op-code map 211 halt_slp 1 1 h andshake 104 , 145 high-frequency system clock 134 i i/o chip select operation 24, 5 1 i /o space 5 C 1 0 , 49 , 51 i 2 c see inter-integrated circuit i eee standard 1149.1 186 C 1 87 iefsee interrupt enable flag ief1 47 C 4 8 , 183 ief2 47 C 4 8 iflg bit 140 , 145 , 148 , 150 C 1 51 , 155 , 157 C 1 58 im 0, op code map 214 im 1, op code map 214 im 2, op code map 214 information page 192 C 1 93 , 196 , 201 , 203 C 2 05 infrared data association 124 encoder/decodersee infrared encoder/de - coder specifications 124 standard 124 standard baud rates 124 transceiver 128 transmit data 12 i nfrared encoder/decoder 12, 38, 124 , 128 r egister 129 s ignal pins 128 input/output request 10 C 11 , 21 , 52 , 54 C 55 , 57 C 58 , 61 assertion delay 232 C 233 deassertion delay 232 C 233 hold time 234 instrd see instruction read indicator instruction read indicator 11 , 21 instruction store 4 0 registers 17 9 i ntel bus mode (multiplexed address and data bus) 61 intel bus mode (separate address and data buses) 57 inter-integrated circuit acknowledge bit 142 , 146 C 148 , 150 C 151 , 155 bus 140 , 144 , 152 bus clock 140 bus protocol 141 clock control register 159 control register 154 data register 154 extended slave address register 153 general characteristics 140 registers 152 serial clock 19 , 23 , 140 C 142 , 159 s erial data 19 , 23 , 140 C 142 , 144 , 151 serial i/o interface 140 slave address register 152 software reset register 160 status register 157 internal pull-up 41
ez80f92/ez80f93 product specification ps015309-1004 preliminary index 246 internal system clock 52 interrupt controller 4 6 i nterrupt enable bit 11, 89 , 107, 15 4 i nterrupt enable fl ag 4 8 , 183 interrupt input 12 C 1 6 , 18 C 1 9 interrupt request 42 C 4 4 , 46 C 4 8 , 83 , 202 interrupt service routine 46 , 48 s pi 46 interrupt vector 46 C 4 7 a ddress 47 C 4 8 interrupt, highest-priority 46 C 4 7 interrupts, edge-selectable 44 introduction to on-chip instrumentation 186 introduction, zilog debug interface 161 iorq see input/output request i r_rxd modulation signal 13 , 125 C 1 2 9 i r_txd modulation signal 12 , 125 , 128 , 12 9 i rdasee infrared data association irq 47 irq_en 83 , 134 , 137 irq_en bit 80 isrsee interrupt service routine ivect 46 , 47 , 48 j jitter, infrared encoder/decoder 12 8 j ta gsee joint t est action group joint t est action group i nterface 186 mode select input 12 , 22 , 187 , 238 m ode selection 18 7 t est clock 12 , 22 , 162 , 186 C 187 , 238 t est data in 12 , 22 , 162 , 187 , 238 t est data out 12 t est mode 1 2 t est trigger output 12 l least-significant bit 84 C 85 , 1 05 , 145 C 146 , 148 , 151, 157 , 163 least-significant byte 47 C 48 , 85 , 159, 175 level-sensitive interrupt input 128 level-sensitive interrupt modes 42 level-sensitive interrupts 44 level- tr iggered interrupts 43 li ne break detection 104 loopback testing, infrared encoder/decoder 128 low-byte vector 46 low-power modes 3 6 l sbsee least-significant bit lsbsee least-significant byte m maskable interrupt 37 s ources 46 v ectors 47 maskable interrupts 4 6 m ass erase operation 196, 201 C 2 02 , 204 C 2 06 mass erase violation 202 master in, slave out 19 , 131 , 133 master mode 132 , 140 , 155 , 157 C 1 60 master mode 150C 151 , 15 6 s tart bit 145 C 147 , 149 C 150 , 152 , 155 C 156 , 158 s top bit 146 C 147 , 149 C 150 , 152 , 155 C 156 , 158 master mode, spi 133 master out, slave in 19 , 131 , 133 master receive 140 , 14 8 m aster transmit mode 140 , 145 master_en bit 133 memory and i/o chip selects 49 memory chip select example 50 memory chip select operation 49 memory chip select priority 50 memory request 10 C 11 , 21 , 49 , 54 C 55 , 57 C 58 , 61 , 230 C 231 hold time 231 memory space 49 , 51 memory write 196 miso see master in, slave out m ode fault 133, 138 mode fault error flag 131 , 133 , 138 m odem status signal 13 C 1 4 , 16 modf see mode fault error flag mosi see master out, slave in most-significant bit 85 C 86 , 1 05 C 1 06 , 131 , 142 , 154 ,
ez80f92/ez80f93 product specification ps015309-1004 preliminary index 247 157 , 163 , 166 , 203 most-significant byte 86 motorola bus mode 64 motorola-compatible 54 mreq see memory request m sbsee most significant bit msbsee most-significant byte multibyte i/o write (row programming) 195 multimaster conflict 133 , 138 n nack see not acknowledge nmi 11 , 22 , 32 , 37 , 46 , 48 , 73 C 7 5 nmi_flag bit 75 nmi_out bit 7 5 n onmaskable interrupt 11 , 32, 37 , 47 C 48 , 73 C 7 5 r eturn from 21 0 n ot acknowledge 142 , 146 C 150 , 155 , 158 o ocisee on-chip instrumentation o n-chip instrumentation 186 activation 186 clock pin 186 information requests 188 interface 187 introduction to 186 pins 187 o n-chip oscillators 218 on-chip pull-up 187 op code maps 211 open source i/o 41 open-drain i/o 41 open-drain mode 41 open-drain output 41 open-drain output 140 open-source mode 4 1 o pen-source output 12 C 1 9 , 41 operating modes 145 operation of the ez80f92 device during zdi breakpoints 167 ordering information 240 overrun error 104 , 106 , 113 , 121 overview, low-power modes 36 p packaging 23 9 p age erase operation 196, 202 C 2 03 , 205 C 2 0 6 p age erase violation 202 part number description 240 pb1 81 phi 19 , 23 pin characteristics 20 pin description 4 pop, op code map 211 , 213 , 215 por see power-on reset p ort x alternate register 1 45 port x alternate register 2 45 port x data direction registers 45 port x data registers 44 power connections 2 power-on reset 33 , 223 and vbo electrical characteristics 223 voltage threshold 223 voltage threshold 33 , 34 precharacterization product 241 program counter 36 C 3 7 , 47 C 4 8 programmable reload timer operation 78 programmable reload timer registers 82 programmable reload timers 77 programmable reload timers overview 77 programming flash memory 194 pull-up resistor, external 41 , 140 push, op code map 211 , 213 , 215 r ram see random access memory r andom access memory 189 address upper byte register 191 control register 191 static 1 , 161 , 198 , 240 rd see read instruction read instruction 10 , 21 , 49 , 52 , 54 , 57 C 58 , 61 assertion delay 230 , 232
ez80f92/ez80f93 product specification ps015309-1004 preliminary index 248 deassertion delay 230 , 232 r eading the current count value 80 real-time clock 12 , 24 , 29 , 33 , 36 , 77 , 88 , 218 , 21 9 a larm 36 , 89 alarm condition 102 a larm control register 102 a larm day-of-the-week register 101 a larm hours register 100 a larm minutes register 99 alarm registers 89 a larm seconds register 98 b attery backup 89 c entury register 97 c ircuit 222 clock source 102 c ontrol register 102 count 89 , 102 count registers 90 c rystal input 11 c rystal output 12 d ay-of-the-month register 94 d ay-of-the-week register 93 h ours register 92 m inutes register 91 m onth register 95 o scillator and source selection 89 o verview 88 p ower supply 12 r ecommended operation 89 r egisters 90 s econds register 90 s ource 73 , 75 , 77 , 81 , 87 supply current 222 supply voltage 222 y ear register 96 receive, infrared encoder/decoder 125 recommended usage of the baud rate generator 109 register map 24 request to send 13 , 15 , 119 , 122 , 128 reset 11 , 21 , 33 C 3 4 , 36 C 3 7 , 41 , 49 , 73 C 7 5 , 89 C 9 0 , 102 , 109 C 1 11 , 129 , 134 , 135 , 172 , 174 , 186 C 1 87 , 189 , 191 , 199 , 201 , 223 reset 33 c ontroller 33 C 3 4 e vent 40 m ode timer 33 o peration 33 o r nmi generation 74 s tates 50 resetting the i 2 c r egisters 152 ri see ring indicator ri0 14 , 128 ri1 17 , 42 ring indicator 14 , 17 , 106 , 119 , 122 trailing edge of 122 r ow program time-out 202 rst_flag bit 74 rtc see real-time clock r tc_unlock 103 rtc_unlock bit 89 , 90 , 102 rtc_ v dd 1 2 , 22 rtc_x in 11 , 22 rtc_x out 12 , 22 rts see request to send rts0 13 rts1 15 rxd0 13 rxd1 15 s s chmitt trigger input 11, 20 sck see spi serial clock s cl see i 2 c serial clock scl line 143 C 1 45 sclk see system clock sda see i 2 c serial data serial bus, spi 139 serial clock 131 , 140 serial clock, i 2 c 1 9 serial clock, spi 18 , 131 serial data 131, 14 0 s erial data, i 2 c 1 9 serial peripheral interface 38 , 46 , 130 C 131 , 133 baud rate generator 134 baud rate generator register 27
ez80f92/ez80f93 product specification ps015309-1004 preliminary index 249 baud rate generator registerslow byte and high byte 135 block 27 control register 27 , 137 data rate 134 flags 133 , 138C 139 functional description 133 interrupt service routine 46 master device 19, 135 master mode 133 mode 18 receive buffer register 27 , 139 registers 135 serial bus 139 signals 131 slave device 19 slave mode 133 status bit 139 status register 27 , 134, 138 transmit shift register 27 , 134C 135 , 139 s etting timer duration 78 shift left arithmetic 147 , 149 , 153 , 210 op code map 212, 216 C 217 shift right arithmetic 210 op code map 212 , 216 s ingle pass mode 77 C 8 0 , 8 2 s ingle-byte i/o write operations 194 sla see shift left arithmetic s lave mode 140 , 151 C 153, 155 , 15 8 s lave mode, spi 133 slave receive 140 , 151 slave select slave select 18 , 131 C 134 , 138 s lave transmit mode 140 , 150 s leep mode 11 , 36 , 102 , 174, 182 , 222 , 223 , 228 sleep-mode recovery 102 sleep-mode recovery reset 24 software break point instruction 186 spi see serial peripheral interface s pi serial clock 18 , 131 idle state 132 pin 133 , 137 receive edge 132 signal 133 transmit edge 132 s pif see serial peripheral interface flags s ra see shift right arithmetic s ram see random access memory , static ss see slave select sta see master mode start bit standard mode 140 start and stop conditions 141 start bit 163 start condition 141 , 143 C 1 44 , 147 C 1 49 , 151 C 1 52 , 155 C 1 60 start condition, zdi 163 starting program counter 47 , 48 stop condition 141 C 1 42 , 144 C 1 45 , 148 , 150 C 1 51 , 155 C 1 56 , 158 C 1 60 stp see master mode stop bit s upply voltage 2 , 33 C 3 4 , 41 , 140 , 221 C 223 switching between bus modes 67 system clock 19 , 33 , 36 C 39, 4 2 C 4 3 , 73 , 75 , 77 , 81 , 109 , 134 , 159 C 1 60 , 167 system clock cycle, cpu 54 C 5 5 , 58 , 61 system clock cycles 11 , 52 C 5 4 , 58 , 62 , 66 , 74 , 186 system clock delay 67 system clock frequency 78 , 81 , 86 , 161C 16 2 s ystem clock oscillator input 17 system clock oscillator output 17 system clock period 187 system clock rising edge 86 , 109 , 134 system clock, high-frequency 134 system clock, internal 52 system reset 11 , 33 t t0_in 17 t1_in 18 t4_out 18 t5_out 19 tck see jtag test clock tdi see jtag test data in tdo see jtag test data out 1 2 , 22 , 187 , 238 teri see ring indicator, trailing edge of test access port 186 test mode 187 time-out period selection 74
ez80f92/ez80f93 product specification ps015309-1004 preliminary index 250 timer 0 in 17 timer 1 in 18 timer control register 82 timer data registerhigh byte 84 timer data registerlow byte 84 timer input source select register 86 timer input source selection 81 timer interrupts 80 timer output 81 timer reload registerhigh byte 86 tms see jtag mode select input trace buffer memory 186 trace history buffer 186 transferring data 142 transmit shift register 105 , 113 , 117 , 120 , 133 transmit shift register, spi 134C 135 , 13 9 t ransmit, infrared encoder/decoder 125 trigout 12 , 22 , 187 txd0 12 txd1 15 u uartsee universal asynchronous receiver/ transmitter universal asynchronous receiver/transmitter baud rate generator register low and high bytes 110 fifo control register 115 functional description 105 functions 105 interrupt enable register 113 interrupt identification register 114 interrupts 106 line control register 116 line status register 120 modem control 106 modem control register 119 modem status interrupt 107 modem status register 121 receive buffer register 112 receiver 106 receiver interrupts 107 recommended usage 108 registers 111 scratch pad register 123 transmit holding register 111 transmitter 105 transmitter interrupt 107 v vbo see voltage brown-out v cc see supply voltage voltage brown-out 33 , 223 protection circuitry 34 reset 34 voltage threshold 33C 34, 223 v oltage, supply 2 , 33 , 34 C 4 1 , 140 , 221 C 2 22 v vbo see voltage brown-out threshold w w ait condition 1 , 11 , 21 , 58 , 61 , 65, 205 wait input signal 52 wait pin, external 54 , 55 wait request 11 wait state 55, 62 , 234 C 2 3 5 t iming for read operations 234 t iming for write operations 23 5 w ait states 47 , 52 C 5 5 , 61 , 70 , 168 , 189 , 199 , 223 C 225 wait states 49, 52 , 199, 22 2 w atch-dog timer 33 , 36 , 73 C 75,167 clock sources 73 C 75 c ontrol register 24, 7 5 o peration 74 o verview 73 r egisters 75 reset 24, 75 r eset register 76 t ime-out 37 , 73 C 76 time-out period 74 , 76 t ime-out reset 2 4 time-out values 74 wcol see write collision w dt see watch-dog timer w r see write instruction
ez80f92/ez80f93 product specification ps015309-1004 preliminary index 251 write collision 133 C 134, 138 s pi 138 write instruction 10 C 11 , 21 , 49 , 52 , 55 , 58 , 61 , 231 , 234 write violation 202 x x in 17 , 23 x out 17 , 23 z z 80 bus mode 54 z80 memory mode 180 , 184 zcl see zilog debug interface clock z da see zilog debug interface data z di_bus_stat 168 , 170 , 184 zdi_busack_en 168 , 184 z disee zilog debug interface 161 C 1 62 , 186 zdi-supported protocol 162 zilog debug interface 161 , 18 6 address match registers 170 block read 167 block write 166 break 173 break control register 171 break mode 183 bus control register 178 bus status register 184 clock 162 C 163 , 165 , 172 clock and data conventions 162 clock frequency 162 clock pin 162 data 162 C 163 , 172 , 187 data pin 162 data transfer 164 debug control 186 debug mode 164 , 178 , 184 master 164 , 166 C 167 , 179 C 180 , 184 master control register 174 read memory register 184 read operations 166 read register low, high, and upper 183 read/write control register 175 read-only registers 170 register addressing 164 register definitions 170 single-bit byte separator 164 single-byte read 166 single-byte write 165 slave 163 , 166 , 167 start command 164 start condition 163 start signal 163 status register 182 write data registers 175 write memory register 180 write operations 165 write-only registers 169
ps015309-1004 preliminary customer feedback form ez80f92/ez80f93 product specification 252 customer feedback form t he ez80f92/ez80f93 product specification if you experience any problems while operating this product, or if you note any inaccuracies while reading this product specification, please copy and complete this form, then mail or fax it to zilog (see return information , below). w e also welcome your suggestions! customer information product information return information zilog system t est/customer support 532 race street san jose, ca 95126 phone: (408) 558-8500 fax: (408) 558-8536 zilog customer support problem description or suggestion provide a complete description of the problem or your suggestion. if you are reporting a specific problem, include all steps leading up to the occurrence of the problem. attach additional pages as necessary . _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ name country company phone address fax city/state/zip email serial # or board fab #/rev. # software version document number host computer description/type

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